@article{oai:ipsj.ixsq.nii.ac.jp:00013435,
 author = {中島, 康彦 and 大野優人 and 竹部, 好正 and Yasuhiko, Nakashima and Yuto, Ohno and Yoshimasa, Takebe},
 issue = {4},
 journal = {情報処理学会論文誌},
 month = {Apr},
 note = {VPP500スカラプロセッサはハードウェア量を抑えつつ複数操作の並列実行を実現するために，3段パイプラインを基本とするLIW方式を採用した．本稿では，VPP500スカラプロセッサの概要および性能測定項目について述べ，次にSPECfp92を用いた測定結果に基づき，VP2600スカラプロセッサと比較しながらVPP500スカラプロセッサについて考察を行う．最後に，浮動小数点演算に要するサイクル数や，キャッシュ容量，ウェイ数を改善することにより，さらに高性能を引き出せることを明らかにする．, This paper describes the scalar processor of the VPP500.The 64-bit long instruction word (LIW) architecture allow the issue of up to three operations every clock cycle.The LIW architecture and the three stage pipeline reduce the hardware cost and branch penalty.We summarize the features of the scalar processor,show the way of performance evaluation,show the results of performance measurement using SPECfp92 benchmark program,and consider about the performance characteristics of the scalar of the VPP500 as compared to the scalar of the VP2600.Finally we show that the shorter cycles of the floating-point operation and the larger multiple-way cache efficiently increase the performance.},
 pages = {863--872},
 title = {VPP500スカラプロセッサの性能},
 volume = {38},
 year = {1997}
}