{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00013144","sets":["581:716:725"]},"path":["725"],"owner":"1","recid":"13144","title":["分散メモリ型マルチプロセッサ用キャッシュ一致保証方式の設計と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"1998-04-15"},"_buckets":{"deposit":"8d825833-7e6b-41d4-9820-42af3a827192"},"_deposit":{"id":"13144","pid":{"type":"depid","value":"13144","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"分散メモリ型マルチプロセッサ用キャッシュ一致保証方式の設計と評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"分散メモリ型マルチプロセッサ用キャッシュ一致保証方式の設計と評価"},{"subitem_title":"Design and Evaluation of the Cache Coherent Mechanism for the Distributed Shared Memory Multi - processor","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"論文","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"1998-04-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"日立製作所新事業推進本部"},{"subitem_text_value":"日立製作所日立研究所"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Business Development Office, Hitachi, Ltd","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Research Laboratory, Hitachi, Ltd","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/13144/files/IPSJ-JNL3904025.pdf"},"date":[{"dateType":"Available","dateValue":"2000-04-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL3904025.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"a0f3f2d1-43bf-4014-a540-52b913382811","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1998 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"森岡, 道雄"},{"creatorName":"黒澤, 憲一"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Michio, Morioka","creatorNameLang":"en"},{"creatorName":"Kenichi, Kurosawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"階層バス型の分散メモリ型マルチプロセッサでは，キャッシュ一致保証方式としてディレクトリ方式を採用するものが多い．これは，分散された各主メモリごとに各主メモリのコピーがどのキャッシュに存在するかを記録する方式である．しかし，この方式では，主メモリ容量の増大にともなってディレクトリの容量が大きくなる問題がある．我々は，商用計算機での実装を前提に，小容量のディレクトリで分散メモリ型マルチプロセッサのキャッシュ一致保証を実現可能な方式を検討した．本論文では，バススヌープ機能とディレクトリ方式を融合させることにより，キャッシュ一致保証を効率良く実装することを狙ったエクスポートディレクトリ方式を提案する．本方式では，マルチプロセッサを複数のクラスタ（複数のプロセッサおよび主メモリからなるグループ）に分割し，各クラスタごとにエクスポートディレクトリを設け，システム全体でキャッシュ一致保証すべきかどうかを判定する方式である．タスクスイッチの影響も含めてOLTPプログラムを評価できるシミュレータを構築し，提案した方式の性能評価を行った．その結果，最適なタスクスケジューリング方式と組み合わせることにより，エクスポートディレクトリ方式によって2倍以上の性能向上が可能であることを明らかにした．","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Directory-based cache coherent mechanism is famous approach for the distributed shared memory multi-processor which has the layered bus architecture.However,when the capacity of the main memory become large,the total size of the directory memory also grows.And it causes a expensive storage hardware for a large scale machine.We investigated the cache coherent mechanism with the small size directory for the commercial multi-processor system.We propose an snoop-based export-directory architecture in order to realize cost-effective cache-coherent mechanism.In this architecture,the system is composed of some clusters which have some processors,a part of the main memory and a export-directory.Theexport-directory is accessed in order to decide inter-cluster or intra-cluster cache coherency for each memory accesses.Proposed architecture are evaluated by trace-driven simulator which can evaluate the OLTP including task activities.The main finding is that the export-directory architecture can improve performance by double in combination with the appropriate task scheduling policy.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1097","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"1088","bibliographicIssueDates":{"bibliographicIssueDate":"1998-04-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"4","bibliographicVolumeNumber":"39"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"マルチプロセッサ"}]},"weko_creator_id":"1"},"id":13144,"updated":"2025-01-23T01:21:48.404047+00:00","links":{},"created":"2025-01-18T22:47:18.695536+00:00"}