{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00130140","sets":["6504:8117:8118"]},"path":["8118"],"owner":"1","recid":"130140","title":["単一仮想記憶の特徴を考慮したスケジューラ構成と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"1996-09-04"},"_buckets":{"deposit":"48fc191c-3ded-476d-93bc-619cf82cce3a"},"_deposit":{"id":"130140","pid":{"type":"depid","value":"130140","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"単一仮想記憶の特徴を考慮したスケジューラ構成と評価","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"単一仮想記憶の特徴を考慮したスケジューラ構成と評価"},{"subitem_title":"A Scheduler Performance for a Single Virtual Address Space Operating System","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1996-09-04","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"(株)東芝 研究開発センター 情報・通信システム研究所"},{"subitem_text_value":"(株)東芝 研究開発センター 情報・通信システム研究所"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Communication and Information Systems Research Labs., R&D Center, TOSHIBA CORPORATION","subitem_text_language":"en"},{"subitem_text_value":"Communication and Information Systems Research Labs., R&D Center, TOSHIBA CORPORATION","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/130140/files/KJ00001341895.pdf"},"date":[{"dateType":"Available","dateValue":"1996-09-04"}],"format":"application/pdf","filename":"KJ00001341895.pdf","filesize":[{"value":"219.1 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"98d56c50-ff5d-482b-90a7-8216faf2fd5a","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々が現在研究開発中のOS(Cubix[CUBe of unIX])では,単一仮想記億空間上で走行するスレッド毎に各領域に対する保護属性を個別に設定可能な保護モデルを採用している. これにより,各スレッドによるデータへのアクセスやプログラム実行に関する保護を安全かつ柔軟な形で実現する枠組みを提供している.こうしたスレッド毎に設定可能なアクセス保護機構を既存の多くのアーキテクチャ上で実現する場合,スレッド単位に個別のページ・テーブルを保持させるという方式が考えられる.本稿では,単一仮想記憶空間において個別の保護空間を有しうるスレッド間でスレッド切り替えが行われる際の最適化を考慮したスケジューリング手法を提案し, これにより効果的に処理される各種操作プリミティブに関する性能評価を提示する.","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"98","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"97","bibliographicIssueDates":{"bibliographicIssueDate":"1996-09-04","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"アーキテクチャサイエンス","bibliographicVolumeNumber":"第53回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"updated":"2025-01-21T00:15:44.097831+00:00","created":"2025-01-19T00:09:15.009237+00:00","links":{},"id":130140}