{"created":"2025-01-19T00:09:05.898904+00:00","updated":"2025-01-21T00:20:00.923111+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00129962","sets":["6504:8103:8115"]},"path":["8115"],"owner":"1","recid":"129962","title":["分散共有メモリでのキャッシュ・コヒーレンシ制御方式"],"pubdate":{"attribute_name":"公開日","attribute_value":"1996-03-06"},"_buckets":{"deposit":"265e475c-571f-4e01-aa7c-e12111aaa574"},"_deposit":{"id":"129962","pid":{"type":"depid","value":"129962","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"分散共有メモリでのキャッシュ・コヒーレンシ制御方式","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"分散共有メモリでのキャッシュ・コヒーレンシ制御方式"},{"subitem_title":"A Cache-Coherence Control Mechanism for A Distributed Shared-Memory System.","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1996-03-06","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"株式会社 東芝 情報・通信システム技術研究所"},{"subitem_text_value":"株式会社 東芝 情報・通信システム技術研究所"},{"subitem_text_value":"株式会社 東芝 情報・通信システム技術研究所"},{"subitem_text_value":"株式会社 東芝 情報・通信システム技術研究所"},{"subitem_text_value":"株式会社 東芝 情報・通信システム技術研究所"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Information and Communication Systems Laboratory,Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Information and Communication Systems Laboratory,Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Information and Communication Systems Laboratory,Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Information and Communication Systems Laboratory,Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Information and Communication Systems Laboratory,Toshiba Corporation","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/129962/files/KJ00001330193.pdf"},"date":[{"dateType":"Available","dateValue":"1996-03-06"}],"format":"application/pdf","filename":"KJ00001330193.pdf","filesize":[{"value":"149.0 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"7b4ab855-2c35-4f87-a50b-53b5e556de6e","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"中規模のマルチプロセッサとして,スヌープキャッシュを備えるマイクロプロセッサを用いたバス結合共有メモリアーキテクチャによるシステムが提案/実用化されている. しかし最近のマイクロプロセッサの高性能化からバスに要求される処理能力の増加,また動作の高速化による実装上の問題から単一のバスに接続できるプロセッサ数の制限が厳しくなってきている. これらの問題に対処する方法として分散共有メモリアーキテクチャを応用することが考えられる.今回我々は,バス結合による分散共有メモリアーキテクチャのシステムにおいて,スヌープキャッシュ/メモリのコヒーレンシ制御を行う方式について提案する.","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"144","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"143","bibliographicIssueDates":{"bibliographicIssueDate":"1996-03-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"並列処理","bibliographicVolumeNumber":"第52回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":129962,"links":{}}