{"updated":"2025-01-21T00:45:16.083851+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00128903","sets":["6504:8089:8100"]},"path":["8100"],"owner":"1","recid":"128903","title":["NANDゲートのみで論理回路を実現する一手法(MA法)"],"pubdate":{"attribute_name":"公開日","attribute_value":"1995-09-20"},"_buckets":{"deposit":"89fce60e-feaa-449b-b2f5-3284f3591aa0"},"_deposit":{"id":"128903","pid":{"type":"depid","value":"128903","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"NANDゲートのみで論理回路を実現する一手法(MA法)","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"NANDゲートのみで論理回路を実現する一手法(MA法)"},{"subitem_title":"A Method for Realizing Logic Circuits with NAND Gates alone(MA)","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1995-09-20","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"富山大学 工学部"},{"subitem_text_value":"富山大学 工学部"},{"subitem_text_value":"京セラ(株)"},{"subitem_text_value":"富山大学 工学部"},{"subitem_text_value":"富山大学 工学部"},{"subitem_text_value":"富山大学 工学部"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Toyama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Toyama University","subitem_text_language":"en"},{"subitem_text_value":"KYOCERA Corporation","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Toyama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Toyama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Toyama University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/128903/files/KJ00001335196.pdf"},"date":[{"dateType":"Available","dateValue":"1995-09-20"}],"format":"application/pdf","filename":"KJ00001335196.pdf","filesize":[{"value":"163.9 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"aa16af33-0340-41bc-bc3b-e4bca79aa323","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"NANDゲートのみによる論理回路の設計は構造の一様性から集積回路化に適し,重要である.(文献[1])では,一線入力多段NANDゲート回路の一設計法(以下MA法と略)を述べているが,そこでは,関数を積和項表現で与え様々な操作を行っている.今回は,積和項表現の代わりにBDD(二分決定グラフ),あるいは,SBDD(共有二分決定グラフ)を用いて効率化できるところは効率化し,多出力関数も扱えるように,拡張している.","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"66","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"65","bibliographicIssueDates":{"bibliographicIssueDate":"1995-09-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第51回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-19T00:08:11.760795+00:00","id":128903,"links":{}}