{"created":"2025-01-19T00:07:25.021032+00:00","updated":"2025-01-21T01:07:30.059189+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00127988","sets":["6504:8078:8087"]},"path":["8087"],"owner":"1","recid":"127988","title":["1.2GFLOPSニューロチップ用S/W開発支援環境の開発"],"pubdate":{"attribute_name":"公開日","attribute_value":"1995-03-15"},"_buckets":{"deposit":"49196e23-ad9c-43c0-a753-1795c62a616b"},"_deposit":{"id":"127988","pid":{"type":"depid","value":"127988","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"1.2GFLOPSニューロチップ用S/W開発支援環境の開発","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"1.2GFLOPSニューロチップ用S/W開発支援環境の開発"},{"subitem_title":"1.2GFLOPS Neural Network Chip Software Development Environment.","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1995-03-15","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"三菱電機(株)半導体基礎研究所"},{"subitem_text_value":"三菱電機(株)半導体基礎研究所"},{"subitem_text_value":"三菱電機(株)半導体基礎研究所"},{"subitem_text_value":"三菱電機(株)半導体基礎研究所"},{"subitem_text_value":"三菱電機(株)半導体基礎研究所"},{"subitem_text_value":"三菱電機(株)半導体基礎研究所"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Mitsubishi Electric Corporation Semiconductor Research Laboratry","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corporation Semiconductor Research Laboratry","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corporation Semiconductor Research Laboratry","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corporation Semiconductor Research Laboratry","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corporation Semiconductor Research Laboratry","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corporation Semiconductor Research Laboratry","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/127988/files/KJ00003118975.pdf"},"date":[{"dateType":"Available","dateValue":"1995-03-15"}],"format":"application/pdf","filename":"KJ00003118975.pdf","filesize":[{"value":"173.7 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"3cee257c-da10-4d99-a51d-ef6ab20d5bb4","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"高性能ニューロプロセッサNEURO4システム用のS/W開発支援環境を開発した。NEURO4は、ニューラルネットワーク演算を高速に実行するために開発された、12個のプロセッシングユニットを有するSIMD型並列処理マイクロプロセッサである。NEURO4チップは、外部拡張ポートを介して通信を行うことで、マルチチップ構成の大規模SIMDシステムを構成できる。S/W開発環境として高級言語とアセンブリ言語が混在するプログラム開発環境を構築中であるが、本稿では、開発を完了したアセンブリ言語でのプログラム開発環境について述べる。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"66","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"65","bibliographicIssueDates":{"bibliographicIssueDate":"1995-03-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第50回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":127988,"links":{}}