{"id":12718,"updated":"2025-01-23T01:31:09.771255+00:00","links":{},"created":"2025-01-18T22:46:59.923043+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00012718","sets":["581:703:712"]},"path":["712"],"owner":"1","recid":"12718","title":["BDD分割を用いたパス・トランジスタ論理の合成"],"pubdate":{"attribute_name":"公開日","attribute_value":"1999-04-15"},"_buckets":{"deposit":"c3b64a7b-b91a-4f49-a8c4-ca886dbd0313"},"_deposit":{"id":"12718","pid":{"type":"depid","value":"12718","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"BDD分割を用いたパス・トランジスタ論理の合成","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"BDD分割を用いたパス・トランジスタ論理の合成"},{"subitem_title":"Synthesis of Pass Transistor Logic Circuits Based on Sliced BDD","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"特集：電子システムの設計技術と設計自動化","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"1999-04-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"神戸大学工学部"},{"subitem_text_value":"神戸大学工学部／現在，川崎製鉄株式会社"},{"subitem_text_value":"神戸大学工学部"},{"subitem_text_value":"神戸大学工学部"},{"subitem_text_value":"神戸大学工学部"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Kobe University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Kobe University/Presently with Kawasaki Steel Corp.","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Kobe University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Kobe University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Kobe University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/12718/files/IPSJ-JNL4004024.pdf"},"date":[{"dateType":"Available","dateValue":"2001-04-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL4004024.pdf","filesize":[{"value":"944.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"243c1556-6db9-4aa3-8cbb-09f861f0f60c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1999 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"高田, 賢吾"},{"creatorName":"井上, 真一"},{"creatorName":"沼, 昌宏"},{"creatorName":"瀧, 和男"},{"creatorName":"平野, 浩太郎"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kengo, Takada","creatorNameLang":"en"},{"creatorName":"Shin-Ichi, Inoue","creatorNameLang":"en"},{"creatorName":"Masahiro, Numa","creatorNameLang":"en"},{"creatorName":"Kazuo, Taki","creatorNameLang":"en"},{"creatorName":"Kotaro, Hirano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"BDD (Binary Decision Diagram)を用いてパス・トランジスタ論理回路を合成する場合  入力変数の数に比例するBDDの段数の増加によって  遅延時間が長くなる. また  \"H\"レベルを回復させるために挿入するバッファの数が増大する. そこで  BDDの任意のレベル区間を分離できるBDD分割を用いたパス・トランジスタ論理の合成手法を提案する. これによりBDDの段数を削減でき  遅延時間と挿入するバッファ数を削減することができる.","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In case of using BDD (Binary Decision Diagram) to synthesize pass transistor logic circuits, the circuit delay and the number of intermediate buffers increase according to the number of BDD stages, which is proportional to the number of primary inputs. We propose a synthesis technique for pass transistor logic based on sliced BDD, which is able to reduce the number of BDD stages, the circuit delay, and the number of transistors.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1564","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"1557","bibliographicIssueDates":{"bibliographicIssueDate":"1999-04-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"4","bibliographicVolumeNumber":"40"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"論理合成"}]},"weko_creator_id":"1"}}