{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00012645","sets":["581:703:711"]},"path":["711"],"owner":"1","recid":"12645","title":["MULHIキャッシュ：VLIWプロセッサのための命令キャッシュ機構"],"pubdate":{"attribute_name":"公開日","attribute_value":"1999-05-15"},"_buckets":{"deposit":"a7166bed-ca05-4f67-8532-40bd4dc55396"},"_deposit":{"id":"12645","pid":{"type":"depid","value":"12645","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"MULHIキャッシュ：VLIWプロセッサのための命令キャッシュ機構","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"MULHIキャッシュ：VLIWプロセッサのための命令キャッシュ機構"},{"subitem_title":"MULHI Cache : An Instruction Cache Mechanism for VLIW Processors","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"特集：並列処理","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"1999-05-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東北大学大学院情報科学研究科"},{"subitem_text_value":"東北大学大学院情報科学研究科"},{"subitem_text_value":"日本アイ・ビー・エム株式会社東京基礎研究所"},{"subitem_text_value":"東北大学大学院情報科学研究科"},{"subitem_text_value":"東北大学大学院情報科学研究科"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"IBM Research, Tokyo Research Laboratory, IBM Japan Ltd","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Tohoku University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/12645/files/IPSJ-JNL4005009.pdf"},"date":[{"dateType":"Available","dateValue":"2001-05-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL4005009.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"3efbc1ac-4f0b-4681-83b8-a1eda58d43d9","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1999 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"仲池, 卓也"},{"creatorName":"阿部, 孝之"},{"creatorName":"大庭, 信之"},{"creatorName":"小林, 広明"},{"creatorName":"中村, 維男"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takuya, Nakaike","creatorNameLang":"en"},{"creatorName":"Takayuki, Abe","creatorNameLang":"en"},{"creatorName":"Nobuyuki, Ooba","creatorNameLang":"en"},{"creatorName":"Hiroaki, Kobayashi","creatorNameLang":"en"},{"creatorName":"Tadao, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"コンパイラによる高度な命令レベル並列性の抽出により高性能を達成するVLIWプロセッサが  次世代プロセッサアーキテクチャとして近年注目を集めている. VLIWプロセッサでは  並列実行可能な複数の演算操作からなる非常に長い命令を高速にフェッチするために  高ヒット率  高バンド幅の命令キャッシュが必要不可欠である. 一般に  VLIW命令中には多くのnop (no operation)が含まれるために  nopを含んだVLIW命令を命令キャッシュに格納すると  命令キャッシュの使用効率が低下し  命令のキャッシュミス率が増加する. そこで  本論文では  VLIWプロセッサのための新たな命令キヤッシュ機構としてMULHI (MULtiple HIt)キャッシュを提案し  SPEC95ベンチマーク中のいくつかのプログラムを用いて性能評価を行う. 性能評価の結果  MULHIキャッシュは  nopを含んだVLIW命令をそのまま格納する従来の命令キャッシュ機構に比べて  最大1.68倍の性能向上を示した.","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"VLIW (Very Long Instruction Word) processors, which are expected to be a next generation high performance microprocessor architecture, need a high-bandwidth, high-hit-rate instruction cache to fetch VLIWs and issue operations of each VLIW to function units quickly. However, when VLIWs including many nops (no operations) are stored in a conventional instruction cache, the cache utilization is not high, resulting in the performance degradation of VLIW processors. In this paper, a new instruction cache mechanism for VLIW processors, named MULHI (MULtiple HIt) cache, is proposed and evaluated using several programs in the SPEC95 benchmark suite. The experimental results indicate that the MULHI cache achieves 1.68 times higher performance than a conventional instruction cache that stores VLIWs with nops.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"2007","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"1996","bibliographicIssueDates":{"bibliographicIssueDate":"1999-05-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"40"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"メモリシステム"}]},"weko_creator_id":"1"},"id":12645,"updated":"2025-01-23T01:32:16.288956+00:00","links":{},"created":"2025-01-18T22:46:56.776924+00:00"}