{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00124822","sets":["6504:8043:8053"]},"path":["8053"],"owner":"1","recid":"124822","title":["多重レジスタリネーミング方式"],"pubdate":{"attribute_name":"公開日","attribute_value":"1993-09-27"},"_buckets":{"deposit":"8ce5bbff-08c7-40b6-b130-bae1cbca3afe"},"_deposit":{"id":"124822","pid":{"type":"depid","value":"124822","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"多重レジスタリネーミング方式","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"多重レジスタリネーミング方式"},{"subitem_title":"Multiple Register-Renaming Method","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1993-09-27","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"富士通研究所"},{"subitem_text_value":"富士通研究所"},{"subitem_text_value":"富士通研究所"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"FUJITSU Laboratories","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU Laboratories","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU Laboratories","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/124822/files/KJ00001339327.pdf"},"date":[{"dateType":"Available","dateValue":"1993-09-27"}],"format":"application/pdf","filename":"KJ00001339327.pdf","filesize":[{"value":"159.6 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"ab97cab4-0c27-4b2b-afb5-adff0646a9ed","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"プロセサの高速化手法の一つであるレジスタリネーミング[1]をハードウェアでインプリメントする場合、Rarc個のアーキテクチャレジスタに対し、それより多いRren個のレジスタを用意して、それらをマッピングするのが普通である。一方、コンパイラがプロセサの性能を充分に引き出すようなコードを生成するためには、レジスタの個数がRarc個では不足に感じることが多い。特に、スーパスカラやVLIWプロセサ等の実行並列度を向上させるためのコードスケジューリングを行なう場合この傾向は顕著になる。我々は、レジスタリネーミングのために用意された余剰なRren-Rarc個のレジスタを有効に活用して、コンパイラが使用できるレジスタ数を実質的に増やす方式である、多重レジスタリネーミング方式を本論文で提案し、その効果について議論する。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"32","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"31","bibliographicIssueDates":{"bibliographicIssueDate":"1993-09-27","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第47回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":124822,"updated":"2025-01-21T02:23:34.098455+00:00","links":{},"created":"2025-01-19T00:04:41.776074+00:00"}