{"updated":"2025-01-21T02:46:35.620802+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00123881","sets":["6504:8032:8041"]},"path":["8041"],"owner":"1","recid":"123881","title":["1チップCPUプロセッサの設計検証(1)CPUプロセッサの機能モデルの開発"],"pubdate":{"attribute_name":"公開日","attribute_value":"1993-03-01"},"_buckets":{"deposit":"106a8ebd-6320-4712-a0bc-a9174a3a3da8"},"_deposit":{"id":"123881","pid":{"type":"depid","value":"123881","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"1チップCPUプロセッサの設計検証(1)CPUプロセッサの機能モデルの開発","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"1チップCPUプロセッサの設計検証(1)CPUプロセッサの機能モデルの開発"},{"subitem_title":"Design Verification of One-Chip CPU Processor(1)Development of CPU Functional Model","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1993-03-01","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"三菱電機(株)"},{"subitem_text_value":"三菱電機(株)"},{"subitem_text_value":"三菱電機(株)"},{"subitem_text_value":"三菱電機(株)"},{"subitem_text_value":"三菱電機(株)"},{"subitem_text_value":"三菱電機(株)"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Mitsubishi Electric Corp.","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corp.","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corp.","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corp.","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corp.","subitem_text_language":"en"},{"subitem_text_value":"Mitsubishi Electric Corp.","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/123881/files/KJ00001337728.pdf"},"date":[{"dateType":"Available","dateValue":"1993-03-01"}],"format":"application/pdf","filename":"KJ00001337728.pdf","filesize":[{"value":"183.8 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"99d145b9-8c90-4d9e-a80d-1d4cd3db896b","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ビジネスコンピュータ用1チップCPUプロセッサを開発した。このチップは、0.8μmCMOSプロセスを用いたフルカスタム設計手法で設計され、約170万Tr.規模のものである。チップ開発は、内蔵される機能の規模・複雑さが増すにつれ、チップ作り直しのリスクが高まる方向にある。このため、開発工程の大幅な後戻りを避けるために、より高品質の設計検証がチップ設計初期から要求されている。今回の開発では、トップダウン設計の観点から、チップの機能仕様および外部仕様を早期に検証するためにハードウェア記述言語であるVerilog-HDLを用いてCPUチップの機能モデルを開発した。本稿では、CPUチップ開発で行われた設計検証のうち、機能検証を中心に機能モデルの概要と機能モデルを利用した検証の効果について報告する。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"150","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"149","bibliographicIssueDates":{"bibliographicIssueDate":"1993-03-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第46回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-19T00:03:53.741725+00:00","id":123881,"links":{}}