{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00121778","sets":["6504:8008:8018"]},"path":["8018"],"owner":"1","recid":"121778","title":["プロセス記述による非同期式制御回路合成システム"],"pubdate":{"attribute_name":"公開日","attribute_value":"1992-02-24"},"_buckets":{"deposit":"7cad815e-313b-451e-a382-7a8b91bcd0f7"},"_deposit":{"id":"121778","pid":{"type":"depid","value":"121778","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"プロセス記述による非同期式制御回路合成システム","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"プロセス記述による非同期式制御回路合成システム"},{"subitem_title":"Synthesis System of Asynchronous Control Circuits based on Process Description","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1992-02-24","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学工学部"},{"subitem_text_value":"東京工業大学工学部"},{"subitem_text_value":"東京工業大学工学部"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/121778/files/KJ00001343466.pdf"},"date":[{"dateType":"Available","dateValue":"1992-02-24"}],"format":"application/pdf","filename":"KJ00001343466.pdf","filesize":[{"value":"209.4 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"2f71aced-eec3-4ec0-a9d4-a15ab3693c36","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年の素子技術はスイッチング遅延が1ピコ秒にせまる高速なデバイスを実現しつつある。しかし従来の同期式プロセッサ回路はチップ全体へのクロック分配が必要であり、配線遅延の相対的な増大によるクロックスキューのため、こうした素子を活用できるような高速のクロックを用いることができない。素子の高速性を有効に活用する一つの方法は、プロセッサを非同期式に構成することである。非同期式回路は、同期式回路の設計にあるような論理設計とチップ設計の相互依存性を排除でき、また、回路を拡張する場合のタイミング設計のやり直しも不要となり拡張性に富むといった利点を持つ。我々は文献[6]で、非同期式制御回路の自動合成手法を提案した。本稿では、この手法を用いた自動合成システムのプロトタイプの作成に関して述べる。まず設計の対象とする非同期回路のモデルについて述べ、次に仕様の記述と合成方式の概要、さらにシステムの構成について述べる。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"160","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"159","bibliographicIssueDates":{"bibliographicIssueDate":"1992-02-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第44回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":121778,"updated":"2025-01-21T03:37:44.924685+00:00","links":{},"created":"2025-01-19T00:02:04.833085+00:00"}