{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00121761","sets":["6504:8008:8018"]},"path":["8018"],"owner":"1","recid":"121761","title":["並列オブジェクト指向トータルアーキテクチャA-NET : ハードウェアの設計方針"],"pubdate":{"attribute_name":"公開日","attribute_value":"1992-02-24"},"_buckets":{"deposit":"e847bd32-375a-44da-9def-1d3c648c66b5"},"_deposit":{"id":"121761","pid":{"type":"depid","value":"121761","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"並列オブジェクト指向トータルアーキテクチャA-NET : ハードウェアの設計方針","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"並列オブジェクト指向トータルアーキテクチャA-NET : ハードウェアの設計方針"},{"subitem_title":"A Parallel Object-Oriented Total Architecture A-NET, : Design Principles","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1992-02-24","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"宇都宮大学工学部"},{"subitem_text_value":"宇都宮大学工学部"},{"subitem_text_value":"宇都宮大学工学部"},{"subitem_text_value":"宇都宮大学工学部"},{"subitem_text_value":"宇都宮大学工学部"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering,Utsunomiya University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering,Utsunomiya University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering,Utsunomiya University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering,Utsunomiya University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering,Utsunomiya University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/121761/files/KJ00001343449.pdf"},"date":[{"dateType":"Available","dateValue":"1992-02-24"}],"format":"application/pdf","filename":"KJ00001343449.pdf","filesize":[{"value":"185.6 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"55db6b8b-903b-48a3-9716-4091da609137","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"A-NET計算機は、並列オブジェクト指向言語A-NETLを高速実行するために設計さかた高並列計算機である。320KBの局所メモリを持つトボロジ独立なノードプロセッサをネットワークにより結合した分散メモリ形態をとり、メッセージ駆動方式でプログラムを実行する。各ノードプロセッサは、メソッドを実行するPEと通信を制御するルータからなる。プロトタイプPEの試作においては、命令セットレペルの設計変更にも柔軟に対応できるよう、LSIピルディングブロックを用いたマイクロプログラム制御方式を採用した。ルー夕は、各種ネットワークトボロジによる結合を可能とするため、ブログラマブル素子を用いて通信制御装置を構成するとともに、ノードプロセッサ間での非同期的なパケット交換に対応できる構成とした。本稿では、A-NET計算機の設計方針とハードウェア構成の概略について述べる。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"126","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"125","bibliographicIssueDates":{"bibliographicIssueDate":"1992-02-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第44回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":121761,"updated":"2025-01-21T03:38:09.311524+00:00","links":{},"created":"2025-01-19T00:02:03.977078+00:00"}