{"id":118890,"created":"2025-01-18T23:59:37.235718+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00118890","sets":["6504:7974:7980"]},"path":["7980"],"owner":"1","recid":"118890","title":["上位階層考慮によるLSIピン割付手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1990-03-14"},"_buckets":{"deposit":"151a1cb2-f21b-4551-9c1a-1505c86a7703"},"_deposit":{"id":"118890","pid":{"type":"depid","value":"118890","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"上位階層考慮によるLSIピン割付手法","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"上位階層考慮によるLSIピン割付手法"},{"subitem_title":"LSI Pin Assignment Method Considering Upper Hierarchical Structure","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1990-03-14","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"(株)日立製作所"},{"subitem_text_value":"(株)日立製作所"},{"subitem_text_value":"(株)日立製作所"},{"subitem_text_value":"(株)日立製作所"},{"subitem_text_value":"(株)日立製作所"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Hitachi Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Ltd.","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/118890/files/KJ00001338511.pdf"},"date":[{"dateType":"Available","dateValue":"1990-03-14"}],"format":"application/pdf","filename":"KJ00001338511.pdf","filesize":[{"value":"133.6 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"785b8eb8-c796-43bc-8951-b7fb30a1350b","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"計算機のより高速化を実現するために,従来のLSI内部の信号ディレイの短縮に着目したレイアウト技術とともに,LSI相互間に渡る信号ディレイの短縮を考慮したLSIピン割付手法が重要になってきている。LSIピン割付とは,LSI相互間を接続する信号について,最適なLSIピンを選択する問題である。特に,ピン割付時,信号ディレイの短縮とともに,各種制約条件の遵守等考慮する項目が多く,問題が複雑である。本稿では,この問題を解決するために,LSIが搭載されるプリント基板上の上位階層の信号の流れとその属性を考慮することにより,信号ディレイ短縮と制約条件遵守等で良好な結果が得られたので報告する。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1341","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"1340","bibliographicIssueDates":{"bibliographicIssueDate":"1990-03-14","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第40回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"updated":"2025-01-21T04:46:28.348485+00:00","links":{}}