{"updated":"2025-01-21T05:11:12.423341+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00117867","sets":["6504:7962:7969"]},"path":["7969"],"owner":"1","recid":"117867","title":["VLSIフロアプランニングにおける端子位置決定問題について"],"pubdate":{"attribute_name":"公開日","attribute_value":"1989-10-16"},"_buckets":{"deposit":"7a687187-580a-413e-a999-4d60dbd8b249"},"_deposit":{"id":"117867","pid":{"type":"depid","value":"117867","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"VLSIフロアプランニングにおける端子位置決定問題について","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"VLSIフロアプランニングにおける端子位置決定問題について"},{"subitem_title":"Determination of pin positions in VLSI floorplanning","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1989-10-16","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"広島大学工学部"},{"subitem_text_value":"広島大学工学部"},{"subitem_text_value":"広島大学工学部"},{"subitem_text_value":"広島大学工学部"},{"subitem_text_value":"広島大学工学部"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Hiroshima University","subitem_text_language":"en"},{"subitem_text_value":"Hiroshima University","subitem_text_language":"en"},{"subitem_text_value":"Hiroshima University","subitem_text_language":"en"},{"subitem_text_value":"Hiroshima University","subitem_text_language":"en"},{"subitem_text_value":"Hiroshima University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/117867/files/KJ00003118202.pdf"},"date":[{"dateType":"Available","dateValue":"1989-10-16"}],"format":"application/pdf","filename":"KJ00003118202.pdf","filesize":[{"value":"159.6 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"b02810b1-d721-4130-9166-2ef10b33a63b","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"著者らは,ビルディングブロック方式のVLSIレイアウト設計における詳細な概略配線とフロアプランを同時に決定する階層化フロアプランニング手法を掟案している.この手法では,(はじめにハードモジュールと,ソフトモジュールの集合に対する概略的な位纏を決定する.次に,階層的にチップ上を長方形に分割しながら,その中に配置されるべきソフトモジュールの部分集合を決定し,同時に詳細な概略配線を決定していく.フロアプランニングが終了した時点で,形状が決定された各ソフトモジュールに至る概略配線経路は,モジュール周辺のスイッチボックスまでのチャネルの系列として求まっている.本稿では,フロアプランニング終了後の各ソフトモジュールに対し,概略配線に基づいて配線長が最小となるようモジュールの端子位置を決定する問題が,モジュールの1次元配置改良問題の拡張として最適に解けることを示す.","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1627","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"1626","bibliographicIssueDates":{"bibliographicIssueDate":"1989-10-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第39回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T23:58:44.779280+00:00","id":117867,"links":{}}