{"id":116803,"updated":"2025-01-21T05:36:39.627794+00:00","links":{},"created":"2025-01-18T23:57:50.670545+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00116803","sets":["6504:7950:7958"]},"path":["7958"],"owner":"1","recid":"116803","title":["マルチベクトルプロセッサVPP結合部の実装方式"],"pubdate":{"attribute_name":"公開日","attribute_value":"1989-03-15"},"_buckets":{"deposit":"770afc29-bc4c-4426-9cce-436fa74fb459"},"_deposit":{"id":"116803","pid":{"type":"depid","value":"116803","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"マルチベクトルプロセッサVPP結合部の実装方式","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチベクトルプロセッサVPP結合部の実装方式"},{"subitem_title":"Considerations On Network Implementation of Multi Vector Processor VPP","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1989-03-15","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東芝総合研究所"},{"subitem_text_value":"東芝総合研究所"},{"subitem_text_value":"東芝総合研究所"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"TOSHIBA Corp. R&D Center","subitem_text_language":"en"},{"subitem_text_value":"TOSHIBA Corp. R&D Center","subitem_text_language":"en"},{"subitem_text_value":"TOSHIBA Corp. R&D Center","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/116803/files/KJ00003117960.pdf"},"date":[{"dateType":"Available","dateValue":"1989-03-15"}],"format":"application/pdf","filename":"KJ00003117960.pdf","filesize":[{"value":"163.9 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"1d5f9d5a-ad61-49aa-ba4e-a30fbe0c5282","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"画像処理をはじめ、様々な分野における高速処理の要求がますます高まってきており、各種並列処理計算機が提案されている。我々は通産省工業技術院が推進している大型プロジェクト「科学技術用高速計算システムの研究開発」の一環として、画像処理を応用の一つとする、高機能並列処理プロセッサVPP(Variable Processor Pipeline)の研究開発を進めている。VPPは第1図に示すごとく、ベクトル演算装置PU(Processor Unit)、共有メモリ等を高速な結合部で結合した、MIMD型の並列計算機である。PUの方式、結合部の制御方式については文献(1),(2),(3)に詳しいので、以下本報告では、この結合部の高速化のための方式上の工夫、および実装上の問題点とその解決方法に焦点をあて説明する。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1444","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"1443","bibliographicIssueDates":{"bibliographicIssueDate":"1989-03-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第38回"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}