{"created":"2025-01-18T23:57:47.446554+00:00","updated":"2025-01-21T05:38:07.604697+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00116740","sets":["6504:7950:7958"]},"path":["7958"],"owner":"1","recid":"116740","title":["MOS論理回路の故障シミュレーションとテスト生成の一方法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1989-03-15"},"_buckets":{"deposit":"d8ee8763-32b4-40d8-803d-4abfb584f64d"},"_deposit":{"id":"116740","pid":{"type":"depid","value":"116740","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"MOS論理回路の故障シミュレーションとテスト生成の一方法","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"MOS論理回路の故障シミュレーションとテスト生成の一方法"},{"subitem_title":"A method of fault simulation and test generation for MOS logical circuits","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1989-03-15","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"防衛大学校"},{"subitem_text_value":"防衛大学校"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"National Defense Academy","subitem_text_language":"en"},{"subitem_text_value":"National Defense Academy","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/116740/files/KJ00003117897.pdf"},"date":[{"dateType":"Available","dateValue":"1989-03-15"}],"format":"application/pdf","filename":"KJ00003117897.pdf","filesize":[{"value":"127.3 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"f83fd280-188d-45eb-8a22-64b246687b6c","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"従来MOS論理回路をタスクとして扱うスイッチレベルシミュレーションの方法を提案しているが、論理値を0、1と不定だけしか定義していなかったため、特に短絡故障においては、実際の故障回路を測定した結果とシミュレーション結果が一致しないことがある。本報告では、タスクモデルによるシミュレーションを拡張したスイッチレベル故障シミュレーションと各故障のためのテスト入力の生成の方法等について提案する。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1320","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"1319","bibliographicIssueDates":{"bibliographicIssueDate":"1989-03-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"ハードウェア","bibliographicVolumeNumber":"第38回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":116740,"links":{}}