{"updated":"2025-01-23T02:06:04.997668+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00011642","sets":["581:664:672"]},"path":["672"],"owner":"1","recid":"11642","title":["リーフセル回路最適化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2002-05-15"},"_buckets":{"deposit":"3f778e4c-6ccb-4e67-9bde-e41e8edcaf5d"},"_deposit":{"id":"11642","pid":{"type":"depid","value":"11642","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"リーフセル回路最適化手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"リーフセル回路最適化手法"},{"subitem_title":"A Circuit Optimization Method for Leaf Cell Design","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"特集：システムLSIの設計技術と設計自動化","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2002-05-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"松下電器産業株式会社半導体先行開発センター"},{"subitem_text_value":"松下電器産業株式会社半導体先行開発センター"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Advanced LSI Technology Development Center, Matsushita Electric Industrial Co., Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Advanced LSI Technology Development Center, Matsushita Electric Industrial Co., Ltd.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/11642/files/IPSJ-JNL4305020.pdf"},"date":[{"dateType":"Available","dateValue":"2004-05-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL4305020.pdf","filesize":[{"value":"321.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"295de2c9-488e-4f34-b292-641b2042f93d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2002 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田中, 正和"},{"creatorName":"福井, 正博"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masakazu, Tanaka","creatorNameLang":"en"},{"creatorName":"Masahiro, Fukui","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"リーフセルの回路最適化において，性能および面積の観点からトランジスタの折り返し段数を最適化する手法について記述する．従来のトランジスタの性能最適化手法では，サイズすなわちゲート幅のみが最適化の対象であり，折り返し段数はレイアウト設計時に性能を考慮せずに決定されていた．一方，本手法では，トランジスタの拡散共有や折り返しが性能および面積に与える影響を推定する手法を利用し，性能最適化の観点からトランジスタサイズだけでなく折り返し段数をも決定する手法について記述する．実験の結果，トランジスタサイズのみを最適化した場合と比較して，ライブラリセルの遅延を最大15%改善できることが分かった．","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents a new method to optimize transistor folding and transistor size for leaf cell design.  Prior works determine transistor folding without considering the performance.  In this method,transistor folding is optimized in account of the performance, using an accurate estimation model for the capacitance of diffusion regions and the layout area considering diffusion sharing or transistor folding.  The experimental results for standard cell libraries show15% delay reduction in the best case from conventional methods.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1329","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"1323","bibliographicIssueDates":{"bibliographicIssueDate":"2002-05-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"43"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"レイアウト設計"}]},"weko_creator_id":"1"},"created":"2025-01-18T22:46:13.102043+00:00","id":11642,"links":{}}