{"updated":"2025-01-23T02:05:29.678986+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00011626","sets":["581:664:672"]},"path":["672"],"owner":"1","recid":"11626","title":["携帯端末用低消費電力H.263 Version 2 コーデックコアのVLSI化設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2002-05-15"},"_buckets":{"deposit":"8171f879-f5ca-4c03-a5fb-fcdd89b8688c"},"_deposit":{"id":"11626","pid":{"type":"depid","value":"11626","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"携帯端末用低消費電力H.263 Version 2 コーデックコアのVLSI化設計","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"携帯端末用低消費電力H.263 Version 2 コーデックコアのVLSI化設計"},{"subitem_title":"Low Power Implementation of H.263 Version 2 Codec Core Dedicated to Mobile Computing","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"特集：システムLSIの設計技術と設計自動化","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2002-05-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"大阪大学大学院情報科学研究科情報システム工学専攻"},{"subitem_text_value":"大阪大学先導的研究オープンセンター"},{"subitem_text_value":"大阪大学大学院情報科学研究科情報システム工学専攻"},{"subitem_text_value":"大阪大学大学院情報科学研究科情報システム工学専攻"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Center for Advanced Research Projects, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/11626/files/IPSJ-JNL4305004.pdf"},"date":[{"dateType":"Available","dateValue":"2004-05-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL4305004.pdf","filesize":[{"value":"386.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e5bc616e-51d6-412f-89af-fdc758ee7b7a","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2002 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"宋天"},{"creatorName":"藤田, 玄"},{"creatorName":"尾上, 孝雄"},{"creatorName":"白川, 功"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tian, Song","creatorNameLang":"en"},{"creatorName":"Gen, Fujita","creatorNameLang":"en"},{"creatorName":"Takao, Onoye","creatorNameLang":"en"},{"creatorName":"Isao, Shirakawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本論文では，小面積H.263 Version 2コーデックのVLSIアーキテクチャとその実装結果に関して記述する．1998年勧告されたH.263 Version2は，既存のH.263に比べ，圧縮率の向上に効果のあるいくつかのオプションを含んでいる．H.263は携帯用途での利用が期待されているが，このH.263 Version 2に特化した専用回路による実装報告例はない．本論文は，そのオプションの中でも比較的ハードウェア規模が少なく，画質向上の大きい，レベル1のオプションを中心とした実装について考察する．実装したレベル1オプションのうち，拡張INTRA符号化モードとデブロッキングフィルタモードに関しては，必要とする機能を可能な限り1モジュールに集積することにより，オプションモードの追加や削減が，該当するモジュールの追加や削減によって実現できるようになったため，応用に応じてハードウェアが容易にカスタム化できる構成となっている．提案したアーキテクチャをVLSI化設計した結果，374 440個のトランジスタを使用し，25MHz動作時に30fps/QCIFの処理速度が実現可能となった．","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper a low power architecture is described for H.263 Version2 codec, which is an extension of the H.263 baseline with 12negotiable modes added to improve the coding performance and toenhance the error resilience. Our implementation is concentrated onthe following 4 modes of the lowest complexity dedicatedly for the mobilecomputing; Advanced INTRA Coding Mode, Deblocking Filter Mode,Modified Quantization Mode, and Supplemental Enhanced Information Mode.Implementation results are also shown to demonstrate that these 4modes have been attained by adding a few area to the H.263 baselineversion.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1170","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"1161","bibliographicIssueDates":{"bibliographicIssueDate":"2002-05-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"43"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"設計事例"}]},"weko_creator_id":"1"},"created":"2025-01-18T22:46:12.409614+00:00","id":11626,"links":{}}