{"created":"2025-01-18T23:55:23.200376+00:00","updated":"2025-01-21T06:46:12.016202+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00113876","sets":["6504:7924:7926"]},"path":["7926"],"owner":"1","recid":"113876","title":["逐次型推論マシンCHI小型化版のハードウェア"],"pubdate":{"attribute_name":"公開日","attribute_value":"1986-10-01"},"_buckets":{"deposit":"4ae4076b-a290-494f-8073-e22db138f989"},"_deposit":{"id":"113876","pid":{"type":"depid","value":"113876","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"逐次型推論マシンCHI小型化版のハードウェア","author_link":[],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"逐次型推論マシンCHI小型化版のハードウェア"},{"subitem_title":"Hardware Design of a CHI Compact Version","subitem_title_language":"en"}]},"item_type_id":"22","publish_date":"1986-10-01","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"日本電気(株)C&Cシステム研究所"},{"subitem_text_value":"日本電気(株)C&Cシステム研究所"},{"subitem_text_value":"日本電気(株)C&Cシステム研究所"}]},"item_22_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"NEC Corporation","subitem_text_language":"en"},{"subitem_text_value":"NEC Corporation","subitem_text_language":"en"},{"subitem_text_value":"NEC Corporation","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/113876/files/KJ00001330682.pdf"},"date":[{"dateType":"Available","dateValue":"1986-10-01"}],"format":"application/pdf","filename":"KJ00001330682.pdf","filesize":[{"value":"191.0 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"e381b376-0945-4e7b-aa6d-5c3e12c29749","displaytype":"detail","licensetype":"license_note"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"通産省第5世代計算機プロジェクトの一環として、高性能PrologマシンCHIの小型化版を開発中である。小型化版CHIは、使用素子をCMLからTTLとCMOSに変更し、1メガビットDRAMを採用することで、デスクサイド・タイプの計算機システムにする予定である。しかし、使用素子を高速のCMLからTTLとCMOSに変更したため、マシン・サイクル・タイムが増加した。マシン・サイクル・タイムの増加は、小型化版CHIの性能を低下する。本稿では、CML版CHIと同性能にすることを目標に、小型化版CHIで新たに導入したハードウェア機能について報告する。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"142","bibliographic_titles":[{"bibliographic_title":"全国大会講演論文集"}],"bibliographicPageStart":"141","bibliographicIssueDates":{"bibliographicIssueDate":"1986-10-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"アーキテクチャおよびハードウェア","bibliographicVolumeNumber":"第33回"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":113876,"links":{}}