{"updated":"2025-01-20T19:30:06.843330+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00113802","sets":["1164:2036:7856:7922"]},"path":["7922"],"owner":"11","recid":"113802","title":["製造ばらつきと配線遅延を同時に考慮した低レイテンシ指向のマルチシナリオ高位合成の評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-02-27"},"_buckets":{"deposit":"9e10e90e-1baf-43c9-a97c-4a0efe0d2b04"},"_deposit":{"id":"113802","pid":{"type":"depid","value":"113802","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"製造ばらつきと配線遅延を同時に考慮した低レイテンシ指向のマルチシナリオ高位合成の評価","author_link":["40551","40549","40550","40548"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"製造ばらつきと配線遅延を同時に考慮した低レイテンシ指向のマルチシナリオ高位合成の評価"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"設計技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2015-02-27","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"現在，早稲田大学基幹理工学部情報理工学科"},{"subitem_text_value":"現在，早稲田大学大学院基幹理工学研究科情報理工学専攻"},{"subitem_text_value":"現在，早稲田大学大学院基幹理工学研究科電子光システム学専攻"},{"subitem_text_value":"現在，早稲田大学大学院基幹理工学研究科情報理工学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Presently with Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Presently with Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Presently with Dept. of Electronic and Photonic Systems, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Presently with Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/113802/files/IPSJ-SLDM15170048.pdf"},"date":[{"dateType":"Available","dateValue":"2017-02-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM15170048.pdf","filesize":[{"value":"911.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"4e194a44-89ab-445b-b0b7-0fb4167ee1da","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"井川, 昂輝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"阿部, 晋矢"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"増大を続ける製造ばらつきや配線遅延への解決策として，HDR アーキテクチャを対象としたマルチシナリオ高位合成手法を提案している．チップ全体をハドルと呼ばれる配線遅延の影響のない範囲に分割することで高位合成段階における適切な配線遅延の予測が可能となる．加えて製造ばらつきによる演算器の遅延ばらつきをシナリオとして扱う．演算器の遅延が Typical ケースの場合の Typical シナリオ，Worst ケースの場合の Worst シナリオを同時に 1 つのチップ上に高位合成し，製造されたチップの特性に応じてシナリオを切り替えることで高い歩留りと高い性能の両立が可能となる．提案手法は各シナリオの動作コントロールステップ数を最小化し，ハドル間データ通信やモジュール間結線をシナリオ間で揃える共通化と呼ばれる処理により全体の面積を削減する．本稿では，計算機実験により各動作条件におけるレイテンシを従来手法と比較し評価する．また，演算器の遅延分布から Typical シナリオで動作可能な確率を算出し，レイテンシの期待値も評価する．提案手法は従来手法と比較し，レイテンシの期待値を最大 35% 削減できることを確認した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2015-02-27","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"48","bibliographicVolumeNumber":"2015-SLDM-170"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:55:19.516543+00:00","id":113802,"links":{}}