{"id":113188,"updated":"2025-01-20T19:44:57.032395+00:00","links":{},"created":"2025-01-18T23:54:49.117579+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00113188","sets":["934:1160:7888"]},"path":["7888"],"owner":"11","recid":"113188","title":["An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-02-12"},"_buckets":{"deposit":"c7700dc2-1a01-4950-a6fe-072da7a1c91f"},"_deposit":{"id":"113188","pid":{"type":"depid","value":"113188","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC","author_link":["37217","37219","37218","37220","37216","37221"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC"},{"subitem_title":"An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[System-Level Design] electronic system level, configurable multi-layer bus, performance estimation","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2015-02-12","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Technology, Osaka University"},{"subitem_text_value":"Graduate School of Information Science and Technology, Osaka University"},{"subitem_text_value":"Graduate School of Information Science and Technology, Osaka University"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, Osaka University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/113188/files/IPSJ-TSLDM0800004.pdf"},"date":[{"dateType":"Available","dateValue":"2015-02-12"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0800004.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6a2b5ea2-ed2a-40e1-a278-18ca68f5cc92","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Salita, Sombatsiri"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yoshinori, Takeuchi"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masaharu, Imai"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Salita, Sombatsiri","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yoshinori, Takeuchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masaharu, Imai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"This paper proposes an efficient performance estimation method for configurable multi-layer bus-based SoC, which evaluates system performance in an early stage of design process. The proposed method uses data flow information obtained from a system-level profiling, an architecture-independent loosely-timed transaction level simulation, and constructs a system-level execution dependency graph. Then, based on each architecture-level model, the architecture-level execution dependency graph is constructed and analyzed to estimate the performance of each architecture. In the analysis, the behavior details of shared buses and multi-layer bus are determined based on the analyzed dynamic bus contention and bus protocols' features. Experiments were conducted by modeling the multi-layer AHB and applying the method to estimate performance of the architectures executing JPEG encoder application. The proposed method estimates the performance of SoC with less than 8% of errors comparing to the results from accurate RTL simulations.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes an efficient performance estimation method for configurable multi-layer bus-based SoC, which evaluates system performance in an early stage of design process. The proposed method uses data flow information obtained from a system-level profiling, an architecture-independent loosely-timed transaction level simulation, and constructs a system-level execution dependency graph. Then, based on each architecture-level model, the architecture-level execution dependency graph is constructed and analyzed to estimate the performance of each architecture. In the analysis, the behavior details of shared buses and multi-layer bus are determined based on the analyzed dynamic bus contention and bus protocols' features. Experiments were conducted by modeling the multi-layer AHB and applying the method to estimate performance of the architectures executing JPEG encoder application. The proposed method estimates the performance of SoC with less than 8% of errors comparing to the results from accurate RTL simulations.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"37","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"26","bibliographicIssueDates":{"bibliographicIssueDate":"2015-02-12","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"8"}]},"relation_version_is_last":true,"weko_creator_id":"11"}}