High-level Synthesis for Low-power Design

• Item type: Trans(1)
• 公開日: 2015-02-12
• タイトル: High-level Synthesis for Low-power Design
• タイトル / 言語: en
• タイトル: High-level Synthesis for Low-power Design
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [High Level Synthesis] high-level synthesis, low-power design, algorithm, compiler optimization, hardware acceleration
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: School of Electrical and Computer Engineering, Cornell University
• 著者所属: Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
• 著者所属: School of Electrical and Computer Engineering, Cornell University
• 著者所属: Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
• 著者所属(英): en
• 著者所属(英): School of Electrical and Computer Engineering, Cornell University
• 著者所属(英): en
• 著者所属(英): Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
• 著者所属(英): en
• 著者所属(英): School of Electrical and Computer Engineering, Cornell University
• 著者所属(英): en
• 著者所属(英): Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
• 著者名: Zhiru, Zhang; Deming, Chen; Steve, Dai; Keith, Campbell
• 著者名(英): Zhiru, Zhang; Deming, Chen; Steve, Dai; Keith, Campbell
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Power and energy efficiency have emerged as first-order design constraints across the computing spectrum from handheld devices to warehouse-sized datacenters. As the number of transistors continues to scale, effectively managing design complexity under stringent power constraints has become an imminent challenge of the IC industry. The manual process of power optimization in RTL design has been increasingly difficult, if not already unsustainable. Complexity scaling dictates that this process must be automated with robust analysis and synthesis algorithms at a higher level of abstraction. Along this line, high-level synthesis (HLS) is a promising technology to improve design productivity and enable new opportunities for power optimization for higher design quality. By allowing early access to the system architecture, high-level decisions during HLS can have a significant impact on the power and energy efficiency of the synthesized design. In this paper, we will discuss the recent research development of using HLS to effectively explore a multi-dimensional design space and derive low-power implementations. We provide an in-depth coverage of HLS low-power optimization techniques and synthesis algorithms proposed in the last decade. We will also describe the key power optimization challenges facing HLS today and outline potential opportunities in tackling these challenges.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Power and energy efficiency have emerged as first-order design constraints across the computing spectrum from handheld devices to warehouse-sized datacenters. As the number of transistors continues to scale, effectively managing design complexity under stringent power constraints has become an imminent challenge of the IC industry. The manual process of power optimization in RTL design has been increasingly difficult, if not already unsustainable. Complexity scaling dictates that this process must be automated with robust analysis and synthesis algorithms at a higher level of abstraction. Along this line, high-level synthesis (HLS) is a promising technology to improve design productivity and enable new opportunities for power optimization for higher design quality. By allowing early access to the system architecture, high-level decisions during HLS can have a significant impact on the power and energy efficiency of the synthesized design. In this paper, we will discuss the recent research development of using HLS to effectively explore a multi-dimensional design space and derive low-power implementations. We provide an in-depth coverage of HLS low-power optimization techniques and synthesis algorithms proposed in the last decade. We will also describe the key power optimization challenges facing HLS today and outline potential opportunities in tackling these challenges.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 8, p. 12-25, 発行日 2015-02-12
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会