{"updated":"2025-01-20T19:44:54.703167+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00113186","sets":["934:1160:7888"]},"path":["7888"],"owner":"11","recid":"113186","title":["Memory and Storage System Design with Nonvolatile Memory Technologies"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-02-12"},"_buckets":{"deposit":"f485a81c-0d9b-4fdf-b528-3c56bb0f19f6"},"_deposit":{"id":"113186","pid":{"type":"depid","value":"113186","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Memory and Storage System Design with Nonvolatile Memory Technologies","author_link":["37202","37207","37205","37201","37204","37206","37200","37203"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Memory and Storage System Design with Nonvolatile Memory Technologies"},{"subitem_title":"Memory and Storage System Design with Nonvolatile Memory Technologies","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[Architectural Design] computer architecture, memory, storage, nonvolatile memory technologies","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2015-02-12","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"University of California, Santa Cruz"},{"subitem_text_value":"Pennsylvania State University"},{"subitem_text_value":"University of California, Santa Barbara"},{"subitem_text_value":"University of California, Santa Barbara"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"University of California, Santa Cruz","subitem_text_language":"en"},{"subitem_text_value":"Pennsylvania State University","subitem_text_language":"en"},{"subitem_text_value":"University of California, Santa Barbara","subitem_text_language":"en"},{"subitem_text_value":"University of California, Santa Barbara","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/113186/files/IPSJ-TSLDM0800002.pdf"},"date":[{"dateType":"Available","dateValue":"2015-02-12"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TSLDM0800002.pdf","filesize":[{"value":"449.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"626293d0-78c7-4f6d-b968-e94e204079ea","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jishen, Zhao"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Cong, Xu"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ping, Chi"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuan, Xie"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jishen, Zhao","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Cong, Xu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ping, Chi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yuan, Xie","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12394951","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-6687","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"The memory and storage system, including processor caches, main memory, and storage, is an important component of various computer systems. The memory hierarchy is becoming a fundamental performance and energy bottleneck, due to the widening gap between the increasing bandwidth and energy demands of modern applications and the limited performance and energy efficiency provided by traditional memory technologies. As a result, computer architects are facing significant challenges in developing high-performance, energy-efficient, and reliable memory hierarchies. New byte-addressable nonvolatile memories (NVMs) are emerging with unique properties that are likely to open doors to novel memory hierarchy designs to tackle the challenges. However, substantial advancements in redesigning the existing memory and storage organizations are needed to realize their full potential. This article reviews recent innovations in rearchitecting the memory and storage system with NVMs, producing high-performance, energy-efficient, and scalable computer designs.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The memory and storage system, including processor caches, main memory, and storage, is an important component of various computer systems. The memory hierarchy is becoming a fundamental performance and energy bottleneck, due to the widening gap between the increasing bandwidth and energy demands of modern applications and the limited performance and energy efficiency provided by traditional memory technologies. As a result, computer architects are facing significant challenges in developing high-performance, energy-efficient, and reliable memory hierarchies. New byte-addressable nonvolatile memories (NVMs) are emerging with unique properties that are likely to open doors to novel memory hierarchy designs to tackle the challenges. However, substantial advancements in redesigning the existing memory and storage organizations are needed to realize their full potential. This article reviews recent innovations in rearchitecting the memory and storage system with NVMs, producing high-performance, energy-efficient, and scalable computer designs.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"11","bibliographic_titles":[{"bibliographic_title":"IPSJ Transactions on System LSI Design Methodology （TSLDM）"}],"bibliographicPageStart":"2","bibliographicIssueDates":{"bibliographicIssueDate":"2015-02-12","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"8"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:54:49.018303+00:00","id":113186,"links":{}}