{"created":"2025-01-18T23:54:48.568435+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00113177","sets":["581:7706:7708"]},"path":["7708"],"owner":"11","recid":"113177","title":["Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-02-15"},"_buckets":{"deposit":"54afbaad-9c5e-4120-9167-7fbde491ac93"},"_deposit":{"id":"113177","pid":{"type":"depid","value":"113177","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension","author_link":["37088","37086","37082","37089","37084","37083","37087","37085"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension"},{"subitem_title":"Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[特集：組込みシステム工学] Dalvik processor, Dalvik hardware extension, Android, Virtual Machine acceleration","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2015-02-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Department of Communications and Computer Engineering, Tokyo Institute of Technology"},{"subitem_text_value":"Department of Communications and Computer Engineering, Tokyo Institute of Technology"},{"subitem_text_value":"Department of Communications and Computer Engineering, Tokyo Institute of Technology"},{"subitem_text_value":"Department of Communications and Computer Engineering, Tokyo Institute of Technology"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Communications and Computer Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Communications and Computer Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Communications and Computer Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Department of Communications and Computer Engineering, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"publish_status":"0","weko_shared_id":11,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/113177/files/IPSJ-JNL5602032.pdf","label":"IPSJ-JNL5602032"},"date":[{"dateType":"Available","dateValue":"2017-02-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL5602032.pdf","filesize":[{"value":"3.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"23fc095b-fb80-4133-a48a-d5b00d8127fd","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2015 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Surachai, Thongkaew"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsuyoshi, Isshiki"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Dongju, Li"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Kunieda"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Surachai, Thongkaew","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsuyoshi, Isshiki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Dongju, Li","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Kunieda","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"The Dalvik virtual machine (Dalvik VM) is an essential piece of software that runs applications on the Android operating system. Android application programs are commonly written in the Java language and compiled to Java bytecode. The Java bytecode is converted to Dalvik bytecode (Dalvik Executable file) which is interpreted by the Dalvik VM on typical Android devices. The significant disadvantage of interpretation is a much slower speed of program execution compared to direct machine code execution on the host CPU. However, there are many techniques to improve the performance of Dalvik VM. A typical methodology is just-in-time compilation which converts frequently executed sequences of interpreted instruction to host machine code. Other methodologies include dedicated bytecode processors and architectural extension on existing processors. In this paper, we propose an alternative methodology, “Fetch & Decode Hardware Extension,” to improve the performance of Dalvik VM. The Fetch & Decode Hardware Extension is a specially designed hardware component to fetch and decode Dalvik bytecode directly, while the core computations within the virtual registers are done by the optimized Dalvik bytecode software handler. The experimental results show the speed improvements on Arithmetic instructions, loop & conditional instructions and method invocation & return instructions, can be achieved up to 2.4x, 2.7x and 1.8x, respectively. The approximate size of the proposed hardware extension is 0.03mm2 (equivalent to 10.56 Kgate) and consumes additional power of only 0.23mW. The stated results are obtained from logic synthesis using the TSMC 90nm technology ＠ 200MHz clock frequency.\n\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.23(2015) No.2 (online)\n------------------------------","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The Dalvik virtual machine (Dalvik VM) is an essential piece of software that runs applications on the Android operating system. Android application programs are commonly written in the Java language and compiled to Java bytecode. The Java bytecode is converted to Dalvik bytecode (Dalvik Executable file) which is interpreted by the Dalvik VM on typical Android devices. The significant disadvantage of interpretation is a much slower speed of program execution compared to direct machine code execution on the host CPU. However, there are many techniques to improve the performance of Dalvik VM. A typical methodology is just-in-time compilation which converts frequently executed sequences of interpreted instruction to host machine code. Other methodologies include dedicated bytecode processors and architectural extension on existing processors. In this paper, we propose an alternative methodology, “Fetch & Decode Hardware Extension,” to improve the performance of Dalvik VM. The Fetch & Decode Hardware Extension is a specially designed hardware component to fetch and decode Dalvik bytecode directly, while the core computations within the virtual registers are done by the optimized Dalvik bytecode software handler. The experimental results show the speed improvements on Arithmetic instructions, loop & conditional instructions and method invocation & return instructions, can be achieved up to 2.4x, 2.7x and 1.8x, respectively. The approximate size of the proposed hardware extension is 0.03mm2 (equivalent to 10.56 Kgate) and consumes additional power of only 0.23mW. The stated results are obtained from logic synthesis using the TSMC 90nm technology ＠ 200MHz clock frequency.\n\n------------------------------\nThis is a preprint of an article intended for publication Journal of\nInformation Processing(JIP). This preprint should not be cited. This\narticle should be cited as: Journal of Information Processing Vol.23(2015) No.2 (online)\n------------------------------","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicIssueDates":{"bibliographicIssueDate":"2015-02-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"56"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":113177,"updated":"2025-01-20T06:44:51.105416+00:00","links":{}}