{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00112995","sets":["6164:6805:6806:7862"]},"path":["7862"],"owner":"10","recid":"112995","title":["並列データ処理基盤を用いた並行バグ並列検査方式の検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-01-10"},"_buckets":{"deposit":"195b994e-8542-44fa-b5e5-fcf57a7d3e3b"},"_deposit":{"id":"112995","pid":{"type":"depid","value":"112995","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"並列データ処理基盤を用いた並行バグ並列検査方式の検討","author_link":["36082"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"並列データ処理基盤を用いた並行バグ並列検査方式の検討"}]},"item_type_id":"18","publish_date":"2014-01-10","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/112995/files/IPSJ-SPRO2013007.pdf"},"date":[{"dateType":"Available","dateValue":"2014-01-10"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SPRO2013007.pdf","filesize":[{"value":"155.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"5"},{"tax":["include_tax"],"price":"0","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e4a731c8-e212-45ad-9f82-f99fbd55f075","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2013 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"荒堀喜貴"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"データ競合やデッドロックに代表される並行処理の不具合（並行バグ）の検査は古典的な問題であり，現在までに多数の検査手法が提案されている．しかし，これらの検査手法のほとんどが現代のチップマルチプロセッサや並列データ処理基盤の登場以前に考案された逐次アルゴリズムに基づいている．そのため，現代的な並列計算環境の活用という観点から見た場合，従来の並行バグ検査方式は性能が十分でない．計算環境の並列化の進展に伴い今後ますます並行処理の普及が進む一方，並行処理の大規模・複雑化とそれによる検査時間の増大が深刻になっており，従来の性能を大幅に上回る並行バグ検査方式が求められている.\nそこで，本研究は，並行バグ検査の基本的な構成要素である動的競合解析に的を絞り，それを現代の並列計算環境に合わせて並列化する方式を検討する．具体的には，動的競合解析の代表であるロックセット解析の並列化を目指し，従来の解析方式が直面する低性能の要因を明らかにした後に，その要因をチップマルチプロセッサ上での並列データ処理技術によって克服する新たな解析方式を検討する．","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"49","bibliographic_titles":[{"bibliographic_title":"夏のプログラミング・シンポジウム2013「ビューティフルデータ」報告集"}],"bibliographicPageStart":"47","bibliographicIssueDates":{"bibliographicIssueDate":"2014-01-10","bibliographicIssueDateType":"Issued"}}]},"relation_version_is_last":true,"weko_creator_id":"10"},"updated":"2025-01-20T19:51:37.547668+00:00","created":"2025-01-18T23:54:39.453803+00:00","links":{},"id":112995}