{"updated":"2025-01-23T02:21:02.780993+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00011234","sets":["581:651:659"]},"path":["659"],"owner":"1","recid":"11234","title":["共通鍵暗号AESの低消費電力論理回路構成法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2003-05-15"},"_buckets":{"deposit":"950db28f-8bce-4dea-a2a3-114353163bb1"},"_deposit":{"id":"11234","pid":{"type":"depid","value":"11234","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"共通鍵暗号AESの低消費電力論理回路構成法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"共通鍵暗号AESの低消費電力論理回路構成法"},{"subitem_title":"A Logic Design Methodology of Low-power AES Cryptographic Circuits","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"論文","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2003-05-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"日本アイ・ビー・エム株式会社東京基礎研究所"},{"subitem_text_value":"日本アイ・ビー・エム株式会社東京基礎研究所"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"IBM Research, Tokyo Research Laboratory, IBM Japan Ltd.","subitem_text_language":"en"},{"subitem_text_value":"IBM Research, Tokyo Research Laboratory, IBM Japan Ltd.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/11234/files/IPSJ-JNL4405016.pdf"},"date":[{"dateType":"Available","dateValue":"2005-05-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL4405016.pdf","filesize":[{"value":"494.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"831f95e3-d54c-41e6-b1fe-5316f415d2dd","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2003 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"森岡, 澄夫"},{"creatorName":"佐藤, 証"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Sumio, Morioka","creatorNameLang":"en"},{"creatorName":"Akashi, Satoh","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"次期米国標準の128ビット共通鍵ブロック暗号AESにおいて，論理設計の工夫によって回路の消費電力を減らす方法を検討した．今回筆者らが行った調査では，AESの消費電力の大半をS-Boxと呼ばれる非線形変換を行う組合せ回路が占めており，S-Boxの消費電力は回路中を伝播するダイナミックハザードの量で決まる．本稿では，消費電力の少ないS-Boxの論理回路構成法（multi-stage PPRM）を提案する．その方法では，合成体上で演算を行うことによって回路規模を減らすとともに，二段論理を何ステージか直列につなげることによって，各ゲートへの信号到達時間を揃えハザード発生を減らす．この結果，これまで知られているS-Box回路と比べて半分から3分の1以下の消費電力を達成した．本手法は，S-Boxにガロア体の逆元演算を用いたその他多くの共通鍵暗号回路にも有効である．","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems.We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of  dynamic hazards.In this paper,we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture.In this S-Box, (i) arithmetic operations are peformed over a composite field in order to reduce the total circuit size,and (ii) each arithmetic operation over sub-fields of the composite field is implemented as PPRM logic (AND-XOR logic) in order to reduce the generation and propagation of dynamic hazards.Low power consumptions of 29uW at 10\\,MHz using 0.13um 1.5V CMOS technology were achieved,while the consumptions of the conventional S-Boxes are two or more times larger.The proposed method is effective in the other common-key ciphers whose S-Boxes use Galois field inversion.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1328","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"1321","bibliographicIssueDates":{"bibliographicIssueDate":"2003-05-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicVolumeNumber":"44"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"セキュリティ基盤技術"}]},"weko_creator_id":"1"},"created":"2025-01-18T22:45:55.302168+00:00","id":11234,"links":{}}