{"links":{},"id":10965,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00010965","sets":["581:638:648"]},"path":["648"],"owner":"1","recid":"10965","title":["詰将棋専用ハードウェアの作成"],"pubdate":{"attribute_name":"公開日","attribute_value":"2004-03-15"},"_buckets":{"deposit":"6c5d1aba-f095-4180-b0b5-f2e22ff49bdf"},"_deposit":{"id":"10965","pid":{"type":"depid","value":"10965","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"詰将棋専用ハードウェアの作成","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"詰将棋専用ハードウェアの作成"},{"subitem_title":"Implementation of Tsume Shogi Hardware","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"論文","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2004-03-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"筑波大学大学院博士課程工学研究科"},{"subitem_text_value":"ビー・ユー・ジー株式会社"},{"subitem_text_value":"筑波大学機能工学系"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Doctoral Program in Engineering, University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"B.U.G., Inc.","subitem_text_language":"en"},{"subitem_text_value":"Institute of Engineering Mechanicsand Systems, University of Tsukuba","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/10965/files/IPSJ-JNL4503035.pdf"},"date":[{"dateType":"Available","dateValue":"2006-03-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL4503035.pdf","filesize":[{"value":"274.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"758fb9ce-c096-4bc6-a960-8e97e3174cc9","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2004 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"堀洋平"},{"creatorName":"斎藤尚徳"},{"creatorName":"丸山勉"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yohei, Hori;HisanoriSaito;TsutomuMaruyama","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"将棋プログラムの棋力の向上のために，専用ハードウェアシステムの開発は必 要不可欠である．本研究ではシステム開発の第1段階として， Field-Programmable Gate Array（FPGA）を使用し詰 将棋の専用ハードウェアの作成を行った． FPGAはユーザ自らが回路構成を変更することのできるLSIであり，また内部に 大容量のRAMを有するため，きわめて並列度の高い演算をチップ内部で実現するこ とができる． この特長を活かし，詰将棋に適した並列・パイプラインアーキテクチャを開発 した．本研究で作成したハードウェアでは，局面情報データを複数のモジュー ルで並列に生成し，これらのデータをパイプライン処理によって指手データ へと変換することで高速な演算を可能にした．また，指手を複数のカテゴリに 分類し，これらを並列・パイプライン処理によって生成することによりさらな る高速化を実現した． 本論文では，詰将棋ハードウェアにおける指手生成の手法とアーキテクチャにつ いて述べた後，実際に問題局面を解いてハードウェアの性能について議論する．","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Developing dedicated hardware systems is an essential approach to improve play strength of shogi programs. To date, use of programmable devices for shogi hardware has been proposed as a feasible method to resolve the problems of high cost and long developing time of hardware implementation. To devise architecture of shogi hardware, we first implemented a tsume shogi solver on a Field-Programmable Gate Array (FPGA). With the ample hardware resource of an FPGA, we implemented highly parallelized architecture on a single chip and realized high-speed computation of tsume-shogi. In this paper, a procedure to generate moves in tsume shogi hardware and its architecture are described.","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1031","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"1014","bibliographicIssueDates":{"bibliographicIssueDate":"2004-03-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"45"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"ゲーム"}]},"weko_creator_id":"1"},"created":"2025-01-18T22:45:43.752505+00:00","updated":"2025-01-23T02:32:18.270407+00:00"}