{"id":107661,"updated":"2025-01-21T08:56:56.975792+00:00","links":{},"created":"2025-01-18T23:50:43.534935+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00107661","sets":["6504:6505:7793"]},"path":["7793"],"owner":"6748","recid":"107661","title":["投機的マルチスレッド実行を行うVLIWマシンによるILPとTLPの活用"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-03-02"},"_buckets":{"deposit":"a9f38c14-eea6-41a2-9268-d09bbff2e6bb"},"_deposit":{"id":"107661","pid":{"type":"depid","value":"107661","revision_id":0},"owners":[6748],"status":"published","created_by":6748},"item_title":"投機的マルチスレッド実行を行うVLIWマシンによるILPとTLPの活用","author_link":["18114","18113","18115","18116"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"投機的マルチスレッド実行を行うVLIWマシンによるILPとTLPの活用"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"22","publish_date":"2011-03-02","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"宇都宮大"},{"subitem_text_value":"宇都宮大"},{"subitem_text_value":"宇都宮大"},{"subitem_text_value":"宇都宮大"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/107661/files/IPSJ-Z73-1H-8.pdf"},"date":[{"dateType":"Available","dateValue":"2014-12-17"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-Z73-1H-8.pdf","filesize":[{"value":"103.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6e368d7c-b9dd-4c21-a8b7-f4606083e6f3","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2011 by the Information Processing Society of Japan"}]},"item_22_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"修沢坤"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"横田隆史"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"大津金光"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"馬場敬信"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"VLIW命令語の中のNOP命令(無操作命令)が多数存在し、VLIWプロセッサの実行ユニット数に応じる単位時間当たりの処理能力が低くなるという問題点がある。この問題に基づいて、アセンブリコートにおいて頻繁に現れる分岐命令の分岐先基本ブロックを投機実行スレッドとして、NOP命令と取り換えて実行できるVLIWアーキテクチャを提案する。この手法ではメインスレッドと一つ或いは二つの投機スレッドを同時に実行し、命令レベルとスレッドレベルの並列性を活かすことができる。また、既存のVLIWプロセッサに少量のハードウェアを追加することで実現できるため、VLIWアーキテクチャ簡素なハードウェア構成という利点を保ちながらVLIWプロセッサの高性能が実現できる。","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"66","bibliographic_titles":[{"bibliographic_title":"第73回全国大会講演論文集"}],"bibliographicPageStart":"65","bibliographicIssueDates":{"bibliographicIssueDate":"2011-03-02","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2011"}]},"relation_version_is_last":true,"weko_creator_id":"6748"}}