{"created":"2025-01-18T23:50:31.231614+00:00","updated":"2025-01-21T09:04:52.229948+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00107318","sets":["1164:2240:7465:7756"]},"path":["7756"],"owner":"11","recid":"107318","title":["自動並列化コンパイラによるソフトウェアキャッシュコヒーレンシ制御手法の評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-12-02"},"_buckets":{"deposit":"f10bece2-b636-41c2-8282-98a0447cd2f1"},"_deposit":{"id":"107318","pid":{"type":"depid","value":"107318","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"自動並列化コンパイラによるソフトウェアキャッシュコヒーレンシ制御手法の評価","author_link":["16604","16602","16603","16605"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"自動並列化コンパイラによるソフトウェアキャッシュコヒーレンシ制御手法の評価"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"コンパイラ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2014-12-02","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学"},{"subitem_text_value":"早稲田大学／現在，日立製作所中央研究所"},{"subitem_text_value":"早稲田大学"},{"subitem_text_value":"早稲田大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"IPSJ","subitem_text_language":"en"},{"subitem_text_value":"IPSJ / Presently with Hitachi Central Research Laboratory","subitem_text_language":"en"},{"subitem_text_value":"IPSJ","subitem_text_language":"en"},{"subitem_text_value":"IPSJ","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/107318/files/IPSJ-HPC14147019.pdf"},"date":[{"dateType":"Available","dateValue":"2016-12-02"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC14147019.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"2008f84d-382a-4857-bfde-aa1919f8eefa","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"岸本, 耀平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"間瀬, 正啓"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"木村, 啓二"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"笠原, 博徳"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"主記憶共有型マルチコアプロセッサにおいて，一般にキャッシュコヒーレンシ制御はハードウェアにより実現されている．今後のプロセッサコア数の増加に伴いキャッシュコヒーレンシハードウェアの回路規模は大きくなり，チップへの実装が困難になること，電力消費が大きくなること，設計期間及び開発費用が増大することが懸念されている．本稿ではこのハードウェアコヒーレンシ制御の問題を解決するために，ハードウェアコヒーレンシ制御機構を持たない主記憶共有型ノンコヒーレントキャッシュマルチコアに対して，並列化コンパイラがソフトウェアに対し自動的にコヒーレンシ制御を行う手法を提案する．本手法を実装した OSCAR 自動並列化コンパイラと，4 コアのクラスタを 2 つ持ちクラスタ間ではハードウェアコヒーレンシを持たない情報家電用マルチコア RP2 を用い性能評価を行った．9 つの科学技術計算アプリケーションを対象として評価を行ったところ，4 コアのハードウェアコヒーレンシ制御使用時の性能は平均で 1 コア性能の 2.80 倍であったのに対し，ハードウェアコヒーレンシを使用せず本手法を適用した 4 コア実行時の性能は平均で 1 コア性能の 2.61 倍となりほぼ同等の速度向上が得られ，さらに 8 コアハードウェアコヒーレンシ制御無効時には平均で 1 コア性能の 3.66 倍とスケールアップすることが確認できた．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-12-02","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"19","bibliographicVolumeNumber":"2014-HPC-147"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":107318,"links":{}}