{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00107315","sets":["1164:2240:7465:7756"]},"path":["7756"],"owner":"11","recid":"107315","title":["FOLCS: FPGAを用いた軽量サイクル・アキュレートNoCシミュレータ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-12-02"},"_buckets":{"deposit":"086cc078-a26f-478c-8853-52771760d8b2"},"_deposit":{"id":"107315","pid":{"type":"depid","value":"107315","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"FOLCS: FPGAを用いた軽量サイクル・アキュレートNoCシミュレータ","author_link":["16593","16594"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FOLCS: FPGAを用いた軽量サイクル・アキュレートNoCシミュレータ"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"シミュレーション","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2014-12-02","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学"},{"subitem_text_value":"東京大学"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/107315/files/IPSJ-HPC14147016.pdf"},"date":[{"dateType":"Available","dateValue":"2016-12-02"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC14147016.pdf","filesize":[{"value":"1.7 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"c9cdcdae-197e-44e2-9d2d-438272a7f88f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"成子, 貴洋"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"平木, 敬"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"マルチコア・メニーコアへの潮流は，コンピュータアーキテクチャのシミュレーションを時間的により困難なものとしている．シミュレーションを実行するホストのコアの速度向上が緩やかであることと，シミュレータの並列化の難しさが原因である．FPGA によるシミュレーションの実行・アクセラレーションは，シミュレーション時間を短縮する有力な手段である．FPGA を用いることの制約は，使用可能なリソースに限りがある点である．本稿は，チップ上のインターコネクションネットワーク (Network on Chip, NoC) に焦点を絞り，FPGA 上で動作する軽量な NoC シミュレータ FOLCS(Flit-Oriented Lightweight Cycle-accurate network Simulator) を提案する．FOLCS は，既存手法よりも少ない FPGA リソースでサイクルアキュレートな NoC シミュレーションを実現する．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-12-02","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"16","bibliographicVolumeNumber":"2014-HPC-147"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:50:31.079479+00:00","updated":"2025-01-21T09:04:47.886628+00:00","id":107315}