{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00107311","sets":["1164:2240:7465:7756"]},"path":["7756"],"owner":"11","recid":"107311","title":["次世代3次元実装メモリのメモリネットワーク構成に関する初期検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-12-02"},"_buckets":{"deposit":"d57b9da5-1fe3-42c1-97e8-0a92cc879823"},"_deposit":{"id":"107311","pid":{"type":"depid","value":"107311","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"次世代3次元実装メモリのメモリネットワーク構成に関する初期検討","author_link":["16583","16580","16581","16582"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"次世代3次元実装メモリのメモリネットワーク構成に関する初期検討"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"メモリ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2014-12-02","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"電気通信大学大学院情報システム学研究科"},{"subitem_text_value":"東京大学大学院情報理工学系研究科"},{"subitem_text_value":"早稲田大学基幹理工学研究科"},{"subitem_text_value":"電気通信大学大学院情報システム学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Systems, The University of Electro-Communications","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Fundamental Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Systems, The University of Electro-Communications","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/107311/files/IPSJ-HPC14147012.pdf"},"date":[{"dateType":"Available","dateValue":"2016-12-02"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC14147012.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"eb804c22-e1d9-4f1c-8026-af56e848b6b5","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"佐々木, 沢"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"近藤, 正章"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"和田, 康孝"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"本多, 弘樹"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Micron 社が中心となって開発を進めている次世代 3 次元実装メモリ Hybrid Memory Cube (HMC) は，シリアル通信を利用した高いデータ転送能力と低い電力消費が評価され，富士通の HPC 向けプロセッサ SPARC64 XIfx での採用が予定されている．しかし，従来に比べ性能あたりのメモリ容量が少ないことが課題である．HMC はロジックチップ内のスイッチを利用したメモリネットワークの構築が可能である．一方で，メモリネットワークにおいて CPU から距離が遠いメモリモジュールへのアクセス遅延が性能に及ぼす影響はまだ十分に解析されていない．本稿では，SPARC 64XIfx のメモリ接続構成を例に，HMC によるメモリネットワークの性能を評価する．また，距離の遠いメモリ上のデータを CPU 近傍の HMC モジュールにキャッシュすることでアクセス遅延を削減する手法を提案し，その効果を評価する．評価の結果，キャッシュ手法が性能向上に寄与する可能性があることを確認した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-12-02","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"12","bibliographicVolumeNumber":"2014-HPC-147"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":107311,"updated":"2025-01-21T09:04:42.408634+00:00","links":{},"created":"2025-01-18T23:50:30.878215+00:00"}