{"updated":"2025-01-21T09:10:16.854174+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00107138","sets":["1164:2036:7423:7746"]},"path":["7746"],"owner":"11","recid":"107138","title":["マルチプレクサ木分割によるフィールドデータ抽出器の構成手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-11-19"},"_buckets":{"deposit":"709b569e-eefe-48ce-88db-4317478a8e08"},"_deposit":{"id":"107138","pid":{"type":"depid","value":"107138","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"マルチプレクサ木分割によるフィールドデータ抽出器の構成手法","author_link":["15773","15765","15768","15772","15771","15770","15767","15774","15766","15769"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチプレクサ木分割によるフィールドデータ抽出器の構成手法"},{"subitem_title":"A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高位合成","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2014-11-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学基幹理工学部情報理工学科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工学専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科電子光システム学専攻"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科情報理工学専攻"},{"subitem_text_value":"富士通研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronic and Photonic Systems, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Computer Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Laboratories Ltd.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/107138/files/IPSJ-SLDM14168039.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM14168039.pdf","filesize":[{"value":"356.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"f9fa7eba-f094-4864-bcfa-12ff5cd5629f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"伊東, 光希"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"川村, 一志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"田宮, 豊"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Koki, Ito","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazushi, Kawamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yutaka, Tamiya","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"TCP/IP オフロードエンジンのパケット解析や動画データエンコード・デコード回路のストリームデータ処理に見られるように，動的にフィールド位置が変わるデータから一部のデータを効率良く取り出す処理が必要となる．これは入出力となるレジスタを多数のマルチプレクサを用いて接続することによって実現されるが，入出力レジスタのバイト長が増大すると，必要となるマルチプレクサ数も増大し，いかにマルチプレクサ数を削減するかが大きな課題となる．マルチプレクサを用いて，M バイト長データを収めるレジスタの任意オフセットから連続した N バイトを読み出す回路をフィールドデータ抽出器と呼ぶ．本稿では，入出力レジスタの接続に仮想中間レジスタを設けることで，マルチプレクサ木の段数を変えずにマルチプレクサ数を削減する回路構成を提案する．また，マルチプレクサ数が最小となるような仮想中間レジスタサイズを定める手法も提案する．提案手法を論理合成して評価したところ，仮想中間レジスタを設ける前と比べてゲート数が最大 92％削減できることを確認した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"As seen in packet analysis of TCP/IP offload engine and stream data processing of encoder/decoder for video data, it is often necessary to extract a part of data from data changed field dynamically , where we can use a field-data extractor. Particularly, an (M, N) field-data extractor reads out any consecutive AT bytes from an M-byte register by connecting its input/output using multiplexers. However, the number of required multiplexers increases too much as the input/output byte lengths increase. How to reduce the number of its required multiplexers is a major challenge. In this paper, we propose an efficient multiplexer-tree configuration method for an (M, N) field-data extractor. Our method is based on inserting a (N + B - 1)-byte virtual intermediate-register into a multiplexer tree and partitioning it into an upper tree and a lower tree. Then our method theoretically reduces the number of required multiplexers without increasing the multiplexer-tree depth. We also propose how to determine the size of the virtual intermediate-register that minimizes the number of required multiplexers. Experimental results show that our method reduces the required number of gates to implement a field-data extractor by up to 92% compared with the one using a naive multiplexer-tree configuration.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-11-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"39","bibliographicVolumeNumber":"2014-SLDM-168"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:50:22.658600+00:00","id":107138,"links":{}}