{"updated":"2025-01-21T09:09:40.309510+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00107120","sets":["1164:2036:7423:7746"]},"path":["7746"],"owner":"11","recid":"107120","title":["DTMOSを用いたサブスレッショルド回路の高速化設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-11-19"},"_buckets":{"deposit":"04be970d-6228-48e1-94a4-a690b8dfbd5f"},"_deposit":{"id":"107120","pid":{"type":"depid","value":"107120","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"DTMOSを用いたサブスレッショルド回路の高速化設計","author_link":["15651","15648","15656","15650","15652","15654","15649","15647","15655","15653"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"DTMOSを用いたサブスレッショルド回路の高速化設計"},{"subitem_title":"High speed design of sub-threshold circuit by using DTMOS","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ディペンダブル","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2014-11-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科／芝浦工業大学工学部情報工学科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Grad. of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Grad. of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Grad. of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Grad. of Science and Engineering, Waseda University / Dept. of Information Science and Engineering, Shibaura Insititute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Grad. of Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/107120/files/IPSJ-SLDM14168021.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM14168021.pdf","filesize":[{"value":"930.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"1b58181e-fa27-4704-ac3e-2c34cf070ff4","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"福留, 祐治"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"史, 又華"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"宇佐美, 公良"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"柳澤, 政生"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuji, Fukudome","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Youhua, Shi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kimiyoshi, Usami","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"サブスレッショルド領域で回路を動作させることで低電力化は実現されるが，同時に速度が劣化するトレードオフの関係にある．本稿ではサブスレッショルド領域において低電力で高速化を実現するため，DTMOS を用いたサブスレッシヨルド回路の高速化設計を行い，トランジスタレベルのシミュレーションの結果，30～45％高速化し，Vdd＝0.2Ｖ, 0.3Ｖ において平均 15％低エネルギー化したことを示す．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Low power consumption is achieved by operating circuits in sub-threshold region. However, in sub-threshold region, the operating speed becomes slow, and the tradeoff between power and speed should be considered carefully. In this work, we present DTMOS implementations to realize high speed and low power in subthreshold region. Transistor level simulation results show that the operating speed can be improved by 30 %-45 %, and on average 15 % energy reduction can be achieved when Vdd ranges 0.2-0.3V.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"5","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-11-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"21","bibliographicVolumeNumber":"2014-SLDM-168"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:50:21.757516+00:00","id":107120,"links":{}}