{"id":10411,"updated":"2025-01-23T02:52:28.041704+00:00","links":{},"created":"2025-01-18T22:45:19.734517+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00010411","sets":["581:612:623"]},"path":["623"],"owner":"1","recid":"10411","title":["チップマルチプロセッサの同期付きキャッシュメモリに対するミスペナルティ隠蔽機構"],"pubdate":{"attribute_name":"公開日","attribute_value":"2006-02-15"},"_buckets":{"deposit":"e6bfa6de-06f3-4a76-9ab5-1d59dbc02789"},"_deposit":{"id":"10411","pid":{"type":"depid","value":"10411","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"チップマルチプロセッサの同期付きキャッシュメモリに対するミスペナルティ隠蔽機構","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"チップマルチプロセッサの同期付きキャッシュメモリに対するミスペナルティ隠蔽機構"},{"subitem_title":"Mechanisms Hiding Miss Penalty for Cache Memory to Shared Variables with Synchronization on a Chip-multiprocessor","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"論文","subitem_subject_scheme":"Other"}]},"item_type_id":"2","publish_date":"2006-02-15","item_2_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州工業大学工学部"},{"subitem_text_value":"九州工業大学工学部"}]},"item_2_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering Kyushu Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering Kyushu Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/10411/files/IPSJ-JNL4702028.pdf"},"date":[{"dateType":"Available","dateValue":"2008-02-15"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-JNL4702028.pdf","filesize":[{"value":"735.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"8"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"5d54e356-10ec-4098-8fdc-9b9d7c4f27c4","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2006 by the Information Processing Society of Japan"}]},"item_2_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山脇, 彰"},{"creatorName":"岩根, 雅彦"}],"nameIdentifiers":[{}]}]},"item_2_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, Yamawaki","creatorNameLang":"en"},{"creatorName":"Masahiko, Iwane","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_2_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00116647","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_2_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7764","subitem_source_identifier_type":"ISSN"}]},"item_2_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"キャッシュミスペナルティの隠蔽はプロセッサの性能向上にとって重要であり，多くの研究がなされてきた．一方，TSVM キャッシュはチップマルチプロセッサにおいて，プロセッサコア間の同期通信を共有変数の一貫性制御と同時に実現し，より効率的な並列処理の実現を目指す．TSVM キャッシュは，タスク，および，スレッド間でのエントリの有効利用を考慮し，アドレスではなくタスクIDとスレッドID からなるタグでラインを指定する．さらに，外部に特殊なメモリを必要としないように，TSVM キャッシュがキャッシングする同期付き共","subitem_description_type":"Other"}]},"item_2_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"To hide cache miss penalty is important for improving a performance of processors. On a chip窶杜ultiprocessor, the TSVM cache performs inter窶菟rocessor communication and synchronization simultaneously with coherence maintenance to make parallel processing mo","subitem_description_type":"Other"}]},"item_2_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"581","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌"}],"bibliographicPageStart":"566","bibliographicIssueDates":{"bibliographicIssueDate":"2006-02-15","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicVolumeNumber":"47"}]},"relation_version_is_last":true,"item_2_alternative_title_2":{"attribute_name":"その他タイトル","attribute_value_mlt":[{"subitem_alternative_title":"計算機アーキテクチャ"}]},"weko_creator_id":"1"}}