{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00103156","sets":["1164:2036:7423:7670"]},"path":["7670"],"owner":"11","recid":"103156","title":["低電力プログラマブル遅延素子と遅延同期回路を用いた製造後クロックスキュー調整手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-09-25"},"_buckets":{"deposit":"4d84a54f-0304-4941-8e79-94bc373a6182"},"_deposit":{"id":"103156","pid":{"type":"depid","value":"103156","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"低電力プログラマブル遅延素子と遅延同期回路を用いた製造後クロックスキュー調整手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"低電力プログラマブル遅延素子と遅延同期回路を用いた製造後クロックスキュー調整手法"},{"subitem_title":"Low-power programmable delay element and clock skew tuning by delay locked loop","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2014-09-25","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"北九州市立大学大学院国際環境工学研究科情報工学専攻"},{"subitem_text_value":"北九州市立大学大学院国際環境工学研究科情報工学専攻"},{"subitem_text_value":"北九州市立大学大学院国際環境工学研究科情報工学専攻"},{"subitem_text_value":"北九州市立大学大学院国際環境工学研究科情報工学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Environmental Engineering, The University of Kitakyushu","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Environmental Engineering, The University of Kitakyushu","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Environmental Engineering, The University of Kitakyushu","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Environmental Engineering, The University of Kitakyushu","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/103156/files/IPSJ-SLDM14167003.pdf"},"date":[{"dateType":"Available","dateValue":"2100-01-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM14167003.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"4e2093ce-caf6-4354-b2d5-b92278c4860e","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"室岡, 大二郎"},{"creatorName":"張, 宇"},{"creatorName":"董, 青"},{"creatorName":"中武, 繁寿"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Daijiro, Murooka","creatorNameLang":"en"},{"creatorName":"Yu, Zhang","creatorNameLang":"en"},{"creatorName":"Qing, Dong","creatorNameLang":"en"},{"creatorName":"Shigetoshi, Nakatake","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"微細化に起因する製造ばらつぎ問題の解決法として，プログラマブル遅延素子 PDE を利用して，チップ製造後に遅延ばらつきを調整するポストシリコンチューニングが知られている．まず本研究では，チャネル分割型 PDE を提案し，その低電力性について報告する．また PDE を伴うクロック木のモデルにおいて，チップ内部に遅延同期回路 DLL を組込み，製造後にチップ外部からフリップフロップ間のスキューを測定し，PDE を調整するため機構の提案し，シミュレーションにより検証する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"For the manufacturing variability due to the miniaturization, the post-silicon tuning of the delay introducing programmable delay elements (PDEs) to mitigate the variability on the delay is prosiming. This paper presents a novel PDE based on the channel length decomposition technique, and reveals that it contributes to the low-power comparing with a conventioanl inverter-chain model. In addition, in a model of a clock tree along with the PDEs, we propose a mechanism for measuring a skew between a pair of filp-flops by introducing a DLL embedded inside the chip. As a result, we appropriately set the PDEs such that the clock tree becomes a zero-skew. The simulation results comparing with the conventional DLL tuning mechanism are also reported.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2014-09-25","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"2014-SLDM-167"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":103156,"updated":"2025-01-21T10:31:24.030032+00:00","links":{},"created":"2025-01-18T23:48:13.998355+00:00"}