{"updated":"2025-01-21T10:41:47.020070+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00102771","sets":["6164:6165:7651:7653"]},"path":["7653"],"owner":"11","recid":"102771","title":["セレクタ論理を適用したバイリニア補間演算器を用いた画像拡大縮小回路のFPGA実装と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-08-21"},"_buckets":{"deposit":"3b6a3941-bf29-4e66-bb2f-03c49185d638"},"_deposit":{"id":"102771","pid":{"type":"depid","value":"102771","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"セレクタ論理を適用したバイリニア補間演算器を用いた画像拡大縮小回路のFPGA実装と評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"セレクタ論理を適用したバイリニア補間演算器を用いた画像拡大縮小回路のFPGA実装と評価"},{"subitem_title":"FPGA Implementation and Evaluation of Image Scaling Circuits Using Seletor-Logic-Based Bi-Linear Interpolation","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高位設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2014-08-21","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/102771/files/IPSJ-DAS2014031.pdf"},"date":[{"dateType":"Available","dateValue":"2016-08-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2014031.pdf","filesize":[{"value":"399.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"bac52e03-714e-4451-810a-ace7e31d6cc3","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"五十嵐, 啓太"},{"creatorName":"柳澤, 政生"},{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Keita, Igarashi","creatorNameLang":"en"},{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"},{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"バイリニア補間は補間演算の 1 つであり，周囲 4 つの値から線形的に値を補間する．画像の拡大・縮小など実用的に用いられることも多い．本稿では，セレクタ論理を利用した新座標の色値を補間する手法について，これを FPGA 上に実装し，その効果を確認する．セレクタ論理の出力値域は必ず 1 以下になるという特性を用いて，桁上げ処理時間を削減する．セレクタ論理を画像処理に適用させることで，補間演算中の積項が減少し，回路面積と遅延が減少する．画像の色値を FPGA ボード上の BRAM に格納し，入力された倍率をもとに新座標を決定する．新座標の色値を補間するために新座標の周囲 4 点に位置する元座標からバイリニア補間演算を行う．補間された色値は再び BRAM に格納され，全ての画素で補間が終了次第，画像拡大縮小処理は終了する．入力画像は BMP 形式であり，色値計算を行う際は RGB を別々に補間演算する．本実装では，RGB 計算を並列計算する．補間演算をビットレベル式変形することで得られた積項をそのまま加算するバイリニア補間演算器を用いた画像処理回路と，補間演算をビットレベル式変形することで得られた積項を減少させたバイリニア補間演算器を用いた画像処理回路を FPGA で実装比較した結果，画像処理回路の最小動作クロック周期は，8.312ns から 7.091ns に削減され，約 15.7 ％の削減が行われた．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Bi-Linear interpolation is one of interpolation techniques, which interpolates a pixel value linearly from its four circumferences and often used for image scaling. In this paper, we pick up a method to interpolate pixels using selector logics and implement and evaluate it on an FPGA board. By applying selector logics to bi-Linear interpolation, total product terms are decreased and thus a circuit are and delay are improved. In our implementation, original pixel values are stored into a memory on the FPGA board and then a new pixel value is interpolated based on an input scaling factor by using bi-linear interpolation. Since the input image is given in BMP format, it has RGB values separately. Then we apply our bi-linear interpolation to each of RGB values on currently. Critical path delay of our bi-linear interpolation using selector logics be comes 7.091ns, whereas it becomes 8.312ns not using selector logics. We realize approximately 15.7% speed-up using selector-logic-based bi-linear interpolation.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"174","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2014論文集"}],"bibliographicPageStart":"169","bibliographicIssueDates":{"bibliographicIssueDate":"2014-08-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2014"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:47:57.206682+00:00","id":102771,"links":{}}