{"updated":"2025-01-21T10:41:23.452032+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00102761","sets":["6164:6165:7651:7653"]},"path":["7653"],"owner":"11","recid":"102761","title":["フロアプランを考慮したマルチプレクサ削減FPGA高位合成手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-08-21"},"_buckets":{"deposit":"1ea25f2d-39e2-4a08-a8f7-3bbd05043d91"},"_deposit":{"id":"102761","pid":{"type":"depid","value":"102761","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"フロアプランを考慮したマルチプレクサ削減FPGA高位合成手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"フロアプランを考慮したマルチプレクサ削減FPGA高位合成手法"},{"subitem_title":"A foorplan-driven FPGA high-level synthesis algorithm for multiplexer reduction","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"高位合成","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2014-08-21","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/102761/files/IPSJ-DAS2014021.pdf"},"date":[{"dateType":"Available","dateValue":"2016-08-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2014021.pdf","filesize":[{"value":"398.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"bf7480c4-879e-43a2-ad2e-56344f955972","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"藤原, 晃一"},{"creatorName":"阿部, 晋矢"},{"creatorName":"川村, 一志"},{"creatorName":"柳澤, 政生"},{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Koichi, Fujiwara","creatorNameLang":"en"},{"creatorName":"Shinya, Abe","creatorNameLang":"en"},{"creatorName":"Kazushi, Kawamura","creatorNameLang":"en"},{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"},{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，画像処理や通信プロトコル処理などデータを高速処理する必要がある場面で，高位合成を利用した FPGA 設計が増加している．既存の FPGA 向け高位合成手法として，FPGA でのモジュールの配置 （フロアプラン） を考慮した手法や，FPGA のマルチプレクサ （MUX） がボトルネックである特徴に着目し MUX を削減する手法がある．しかし，モジュールの配置と MUX の削減を同時に実現する手法は提案されていない．本稿では，FPGA 設計に HDR アーキテクチャを採用し，MUX を削減・制限する高位合成手法を提案する．提案手法では，レジスタ分散型アーキテクチャである HDR アーキテクチャを用いて，高位合成段階でモジュールの配置を考慮し，配線遅延を見積もる．また演算器バインディングでは MUX 数の削減を，レジスタバインディングでは MUX の入力数の制限を実現する．提案手法を計算機上に実装し，従来手法と比較した結果，スライス数を最大 38%，平均 17%削減，遅延を最大 9%，平均 5%削減を実現した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently, high-level synthesis (HLS) techniques for FPGA designs are required in reconfigurable network processing and image processing. Conventional HLS algorithms for FPGA designs realize either module floorplan-driven HLS or reducing multiplexer's cost but no HLS algorithm targeting FPGAs realizes both of them. In this paper, we propose a floorplan-driven high-level synthesis algorithm for multiplexer reduction. By utilizing a distirbuted-register architecture called HDR architecture, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose a novel binding method called datapath-oriented scheduling/FU binding and utilize datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 38% and circuit delay by up to 9% compared with the conventional approach.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"114","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2014論文集"}],"bibliographicPageStart":"109","bibliographicIssueDates":{"bibliographicIssueDate":"2014-08-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2014"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:47:56.717134+00:00","id":102761,"links":{}}