{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00102760","sets":["6164:6165:7651:7653"]},"path":["7653"],"owner":"11","recid":"102760","title":["ニアスレッショルド電圧動作に適した単一電源で動作する高歩留まりオンチップメモリの設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-08-21"},"_buckets":{"deposit":"7a864bb3-7c3e-4bfe-8b9c-6e22b28e8571"},"_deposit":{"id":"102760","pid":{"type":"depid","value":"102760","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"ニアスレッショルド電圧動作に適した単一電源で動作する高歩留まりオンチップメモリの設計","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ニアスレッショルド電圧動作に適した単一電源で動作する高歩留まりオンチップメモリの設計"},{"subitem_title":"High Yield On-Chip Memory Design for Single Supply Near-Threshold Computing","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"低消費電力設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2014-08-21","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"},{"subitem_text_value":"京都大学大学院情報学研究科"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Kyoto University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/102760/files/IPSJ-DAS2014020.pdf"},"date":[{"dateType":"Available","dateValue":"2016-08-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2014020.pdf","filesize":[{"value":"302.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"2b991a1f-5904-4a14-b9ae-96a216bdff8d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"塩見, 準"},{"creatorName":"石原, 亨"},{"creatorName":"小野寺, 秀俊"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jun, Shiomi","creatorNameLang":"en"},{"creatorName":"Tohru, Ishihara","creatorNameLang":"en"},{"creatorName":"Hidetoshi, Onodera","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"集積回路中のオンチップメモリは集積回路全体の消費エネルギーの中で大きな割合を占めており，低消費エネルギーを実現するオンチップメモリが求められている．従って，電源電圧を低くすることがオンチップメモリにも求められている．本稿では，ニアスレッショルド領域で動作するエネルギー効率の高い高歩留まりオンチップメモリの設計・評価実験を行う．商用 28 nm プロセスでの比較結果，設計したメモリは従来の SRAM 構造より読み出し操作で約 40%省エネルギーであることが示された．また，商用プロセスのモンテカルロシミュレーションを行った結果，設計した回路の 5σ 遅延が SRAM 構造より小さいことがわかった．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"On-chip memory is one of the most energy consuming components in today's LSI. Aggressive voltage scaling is thus applied to the memory to the memory to obtain a quadratic reduction of dynamic energy consumption, which drastically degrades the memory yields. This paper discusses a design methodology for a high yield on-chip memory which uses a single near-threshold supply voltage. This memory has an energy-efficient readout structure in near-threshold operation. Circuit simulation using a commercial 28nm process technology shows that the energy consumed in our memory for readout operation is about 40% more energy efficient than that of a conventional SRAM readout structure. Circuit simulation using a foundry provided Monte Carlo simulation package also shows that the 5σ worst case read-access time of our originally designed memory is smaller than that of a conventional SRAM circuit.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"108","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2014論文集"}],"bibliographicPageStart":"103","bibliographicIssueDates":{"bibliographicIssueDate":"2014-08-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2014"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"updated":"2025-01-21T10:41:21.166295+00:00","created":"2025-01-18T23:47:56.668575+00:00","links":{},"id":102760}