{"updated":"2025-01-21T10:41:03.919826+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00102752","sets":["6164:6165:7651:7653"]},"path":["7653"],"owner":"11","recid":"102752","title":["遅延ばらつき許容量を調整できるRDRアーキテクチャ向け高位合成手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-08-21"},"_buckets":{"deposit":"eaa12ff7-e3aa-41e4-bd33-dbd99a191417"},"_deposit":{"id":"102752","pid":{"type":"depid","value":"102752","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"遅延ばらつき許容量を調整できるRDRアーキテクチャ向け高位合成手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"遅延ばらつき許容量を調整できるRDRアーキテクチャ向け高位合成手法"},{"subitem_title":"A High-Level Synthesis Algorithm with Delay Variation Tolerance Adjustment for RDR Architectures","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ばらつき","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2014-08-21","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"},{"subitem_text_value":"早稲田大学大学院基幹理工学研究科"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Waseda University","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/102752/files/IPSJ-DAS2014012.pdf"},"date":[{"dateType":"Available","dateValue":"2016-08-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2014012.pdf","filesize":[{"value":"490.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"330","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"2bd0fec6-740b-4464-818f-23335d6f8238","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"萩尾, 勇太"},{"creatorName":"柳澤, 政生"},{"creatorName":"戸川, 望"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yuta, Hagio","creatorNameLang":"en"},{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"},{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"LSI の微細加工技術の進歩により，配線遅延の拡大や製造時の遅延ばらつきによるタイミング違反が問題となっている．とりわけ配線遅延がゲート遅延と比較して相対的に増加しており，高位合成段階でいかに配線遅延を取り扱うかが鍵となる．また，製造時の遅延ばらつきに対応するために，従来は過剰なマージンの挿入，統計的静的遅延解析などが適用されてきたが，近年は性能低下しない手法としてチップ製造後の回路チューニングが提案されている．このような背景に基づき，本稿では遅延ばらつきの許容量を調整できる RDR アーキテクチャ向け高位合成手法を提案する．遅延ばらつきによるタイミング違反が発生しない場合と発生した場合の 2 通りのスケジューリング，バインディングを想定することで，配線遅延の拡大と製造時の遅延ばらつきに対応した高位合成を実現する．入力としてばらつき率を与えることで，ばらつきの許容量を調整する．また，RDR アーキテクチャの空き領域を利用しここに演算器を追加することで，遅延ばらつきによるタイミング違反が発生した場合でも実行時間の最小化を図る．さらに，2 通りのスケジューリング，バインディング結果に類似化という考えを導入することでチップ面積を最小化する．計算機実験により，提案手法は従来手法と比較して遅延ばらつき発生時の実行時間を最大 32.3 %削減できることを確認した．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a high-level synthesis algorithm with delay variation tolerance adjustment for RDR architectures. We first obtain a non-delayed scheduling/binding result and a delayed scheduling/binding result independently. When we obtain a delayed scheduling/binding result, we use variation rate. By adding several extra functional units to vacant RDR islands, we have a delayed scheduling/binding result so that its latency cannot be increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 32.3% compared with the conventional approach.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"60","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2014論文集"}],"bibliographicPageStart":"55","bibliographicIssueDates":{"bibliographicIssueDate":"2014-08-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2014"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"created":"2025-01-18T23:47:56.273883+00:00","id":102752,"links":{}}