{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00102578","sets":["934:1119:7515:7642"]},"path":["7642"],"owner":"11","recid":"102578","title":["Design Aid of Multi-core Embedded Systems with Energy Model"],"pubdate":{"attribute_name":"公開日","attribute_value":"2014-08-19"},"_buckets":{"deposit":"0fe83b90-da95-4928-b3ea-2aef9eac0dea"},"_deposit":{"id":"102578","pid":{"type":"depid","value":"102578","revision_id":0},"owners":[11],"status":"published","created_by":11},"item_title":"Design Aid of Multi-core Embedded Systems with Energy Model","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Design Aid of Multi-core Embedded Systems with Energy Model"},{"subitem_title":"Design Aid of Multi-core Embedded Systems with Energy Model","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"[組込みシステム] low power, multi-core embedded systems, energy model","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2014-08-19","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo"},{"subitem_text_value":"The University of Tokyo/Presently with NoConsulting"},{"subitem_text_value":"The University of Tokyo/Presently with DeNA Co., Ltd."},{"subitem_text_value":"The University of Tokyo"},{"subitem_text_value":"Renesas Electronics Corporation"},{"subitem_text_value":"Renesas Electronics Corporation"},{"subitem_text_value":"Renesas Electronics Corporation"},{"subitem_text_value":"Renesas Electronics Corporation"},{"subitem_text_value":"The University of Tokyo"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo / Presently with NoConsulting","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo / Presently with DeNA Co., Ltd.","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Renesas Electronics Corporation","subitem_text_language":"en"},{"subitem_text_value":"Renesas Electronics Corporation","subitem_text_language":"en"},{"subitem_text_value":"Renesas Electronics Corporation","subitem_text_language":"en"},{"subitem_text_value":"Renesas Electronics Corporation","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/102578/files/IPSJ-TACS0703006.pdf"},"date":[{"dateType":"Available","dateValue":"2016-08-19"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TACS0703006.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"3e9bd76e-53f6-4f4d-b6e4-0b540772d670","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2014 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takashi, Nakada"},{"creatorName":"Kazuya, Okamoto"},{"creatorName":"Toshiya, Komoda"},{"creatorName":"Shinobu, Miwa"},{"creatorName":"Yohei, Sato"},{"creatorName":"Hiroshi, Ueki"},{"creatorName":"Masanori, Hayashikoshi"},{"creatorName":"Toru, Shimizu"},{"creatorName":"Hiroshi, Nakamura"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takashi, Nakada","creatorNameLang":"en"},{"creatorName":"Kazuya, Okamoto","creatorNameLang":"en"},{"creatorName":"Toshiya, Komoda","creatorNameLang":"en"},{"creatorName":"Shinobu, Miwa","creatorNameLang":"en"},{"creatorName":"Yohei, Sato","creatorNameLang":"en"},{"creatorName":"Hiroshi, Ueki","creatorNameLang":"en"},{"creatorName":"Masanori, Hayashikoshi","creatorNameLang":"en"},{"creatorName":"Toru, Shimizu","creatorNameLang":"en"},{"creatorName":"Hiroshi, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11833852","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7829","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Shifting to multi-core designs is so pervasive a trend to overcome the power wall and it is a necessary move for embedded systems in our rapidly evolving information society. Meanwhile, the need to increase the battery life and reduce maintenance costs for such embedded systems is very critical. Therefore, a wide variety of power reduction techniques have been proposed and realized, including Clock Gating, DVFS and Power Gating. To maximize the effectiveness of these techniques, task scheduling is a key but for multi-core systems it is very complicated due to the huge exploration space. This problem is a major obstacle for further power reduction. To cope with it, we propose a design method for embedded systems to minimize their energy consumption under performance constraints. This method is based on the clarification of properties of the above mentioned low power techniques and their interactions. In more details, we firstly establish energy models for these low power techniques and our target systems. We then explore for the best configuration by constructing an optimization problem especially for applications which have a longer deadline than the execution interval. Finally, we propose an approximate solution using dynamic programming with a lower computation complexity and compare it to a brute force explicit solution. We confirm with our evaluations that the proposed method successfully found a better configuration which reduces the total energy consumption by 32% if compared to the manually optimized configuration, which utilizes only one core.","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Shifting to multi-core designs is so pervasive a trend to overcome the power wall and it is a necessary move for embedded systems in our rapidly evolving information society. Meanwhile, the need to increase the battery life and reduce maintenance costs for such embedded systems is very critical. Therefore, a wide variety of power reduction techniques have been proposed and realized, including Clock Gating, DVFS and Power Gating. To maximize the effectiveness of these techniques, task scheduling is a key but for multi-core systems it is very complicated due to the huge exploration space. This problem is a major obstacle for further power reduction. To cope with it, we propose a design method for embedded systems to minimize their energy consumption under performance constraints. This method is based on the clarification of properties of the above mentioned low power techniques and their interactions. In more details, we firstly establish energy models for these low power techniques and our target systems. We then explore for the best configuration by constructing an optimization problem especially for applications which have a longer deadline than the execution interval. Finally, we propose an approximate solution using dynamic programming with a lower computation complexity and compare it to a brute force explicit solution. We confirm with our evaluations that the proposed method successfully found a better configuration which reduces the total energy consumption by 32% if compared to the manually optimized configuration, which utilizes only one core.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"46","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌コンピューティングシステム(ACS)"}],"bibliographicPageStart":"37","bibliographicIssueDates":{"bibliographicIssueDate":"2014-08-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"7"}]},"relation_version_is_last":true,"weko_creator_id":"11"},"id":102578,"updated":"2025-01-21T10:45:03.518727+00:00","links":{},"created":"2025-01-18T23:47:50.271385+00:00"}