Design Aid of Multi-core Embedded Systems with Energy Model

• Item type: Trans(1)
• 公開日: 2014-08-19
• タイトル: Design Aid of Multi-core Embedded Systems with Energy Model
• タイトル / 言語: en
• タイトル: Design Aid of Multi-core Embedded Systems with Energy Model
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [組込みシステム] low power, multi-core embedded systems, energy model
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: The University of Tokyo
• 著者所属: The University of Tokyo／Presently with NoConsulting
• 著者所属: The University of Tokyo／Presently with DeNA Co., Ltd.
• 著者所属: The University of Tokyo
• 著者所属: Renesas Electronics Corporation
• 著者所属: Renesas Electronics Corporation
• 著者所属: Renesas Electronics Corporation
• 著者所属: Renesas Electronics Corporation
• 著者所属: The University of Tokyo
• 著者所属(英): en
• 著者所属(英): The University of Tokyo
• 著者所属(英): en
• 著者所属(英): The University of Tokyo / Presently with NoConsulting
• 著者所属(英): en
• 著者所属(英): The University of Tokyo / Presently with DeNA Co., Ltd.
• 著者所属(英): en
• 著者所属(英): The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Renesas Electronics Corporation
• 著者所属(英): en
• 著者所属(英): Renesas Electronics Corporation
• 著者所属(英): en
• 著者所属(英): Renesas Electronics Corporation
• 著者所属(英): en
• 著者所属(英): Renesas Electronics Corporation
• 著者所属(英): en
• 著者所属(英): The University of Tokyo
• 著者名: Takashi, Nakada; Kazuya, Okamoto; Toshiya, Komoda; Shinobu, Miwa; Yohei, Sato; Hiroshi, Ueki; Masanori, Hayashikoshi; Toru, Shimizu; Hiroshi, Nakamura
• 著者名(英): Takashi, Nakada; Kazuya, Okamoto; Toshiya, Komoda; Shinobu, Miwa; Yohei, Sato; Hiroshi, Ueki; Masanori, Hayashikoshi; Toru, Shimizu; Hiroshi, Nakamura
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Shifting to multi-core designs is so pervasive a trend to overcome the power wall and it is a necessary move for embedded systems in our rapidly evolving information society. Meanwhile, the need to increase the battery life and reduce maintenance costs for such embedded systems is very critical. Therefore, a wide variety of power reduction techniques have been proposed and realized, including Clock Gating, DVFS and Power Gating. To maximize the effectiveness of these techniques, task scheduling is a key but for multi-core systems it is very complicated due to the huge exploration space. This problem is a major obstacle for further power reduction. To cope with it, we propose a design method for embedded systems to minimize their energy consumption under performance constraints. This method is based on the clarification of properties of the above mentioned low power techniques and their interactions. In more details, we firstly establish energy models for these low power techniques and our target systems. We then explore for the best configuration by constructing an optimization problem especially for applications which have a longer deadline than the execution interval. Finally, we propose an approximate solution using dynamic programming with a lower computation complexity and compare it to a brute force explicit solution. We confirm with our evaluations that the proposed method successfully found a better configuration which reduces the total energy consumption by 32% if compared to the manually optimized configuration, which utilizes only one core.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Shifting to multi-core designs is so pervasive a trend to overcome the power wall and it is a necessary move for embedded systems in our rapidly evolving information society. Meanwhile, the need to increase the battery life and reduce maintenance costs for such embedded systems is very critical. Therefore, a wide variety of power reduction techniques have been proposed and realized, including Clock Gating, DVFS and Power Gating. To maximize the effectiveness of these techniques, task scheduling is a key but for multi-core systems it is very complicated due to the huge exploration space. This problem is a major obstacle for further power reduction. To cope with it, we propose a design method for embedded systems to minimize their energy consumption under performance constraints. This method is based on the clarification of properties of the above mentioned low power techniques and their interactions. In more details, we firstly establish energy models for these low power techniques and our target systems. We then explore for the best configuration by constructing an optimization problem especially for applications which have a longer deadline than the execution interval. Finally, we propose an approximate solution using dynamic programming with a lower computation complexity and compare it to a brute force explicit solution. We confirm with our evaluations that the proposed method successfully found a better configuration which reduces the total energy consumption by 32% if compared to the manually optimized configuration, which utilizes only one core.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11833852
• 書誌情報: 情報処理学会論文誌コンピューティングシステム（ACS）; 巻 7, 号 3, p. 37-46, 発行日 2014-08-19
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7829
• 出版者 / 言語: ja
• 出版者: 情報処理学会