A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency

• Item type: Trans(1)
• 公開日: 2014-08-04
• タイトル: A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency
• タイトル / 言語: en
• タイトル: A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [System-Level Optimization] 3D NoC, fully adaptive, routing algorithm
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Information, Productions and Systems, Waseda University
• 著者所属: Graduate School of Information, Productions and Systems, Waseda University
• 著者所属: Graduate School of Information, Productions and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information, Productions and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information, Productions and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information, Productions and Systems, Waseda University
• 著者名: Xin, Jiang; Lian, Zeng; Takahiro, Watanabe
• 著者名(英): Xin, Jiang; Lian, Zeng; Takahiro, Watanabe
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: With rapid progress in Integrated Circuit technologies, Three-Dimensional Network-on-Chips (3DNoCs) have become a promising solution for achieving low latency and low power. Under the constraint of the TSV number used in 3DNoCs, designing a proper routing algorithm with fewer TSVs is a critical problem for network performance improvement. In this work, we design a novel fully adaptive routing algorithm in 3D NoC. The algorithm consists of two parts: one is a vertical node assignment in inter-layer routing, which is a TSV selection scheme in a limited quantity of TSVs in the NoC architecture, and the other is a 2D fully adaptive routing algorithm in intra-layer routing, which combines the optimization of routing distance, network traffic condition and diversity of the path selection. Simulation results show that our proposed routing algorithm can achieve lower latency and energy consumption compared with other traditional routing algorithms.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: With rapid progress in Integrated Circuit technologies, Three-Dimensional Network-on-Chips (3DNoCs) have become a promising solution for achieving low latency and low power. Under the constraint of the TSV number used in 3DNoCs, designing a proper routing algorithm with fewer TSVs is a critical problem for network performance improvement. In this work, we design a novel fully adaptive routing algorithm in 3D NoC. The algorithm consists of two parts: one is a vertical node assignment in inter-layer routing, which is a TSV selection scheme in a limited quantity of TSVs in the NoC architecture, and the other is a 2D fully adaptive routing algorithm in intra-layer routing, which combines the optimization of routing distance, network traffic condition and diversity of the path selection. Simulation results show that our proposed routing algorithm can achieve lower latency and energy consumption compared with other traditional routing algorithms.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 7, p. 101-109, 発行日 2014-08-04
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会