Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating

• Item type: Trans(1)
• 公開日: 2014-08-04
• タイトル: Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating
• タイトル / 言語: en
• タイトル: Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [Behavioral Synthesis] high-level synthesis, huddle-based distributed register architecture, multi-stage clock gating, clock gating timing, gating step count
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属: Department of Electronic and Photonic Systems, Waseda University
• 著者所属: Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Electronic and Photonic Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science and Engineering, Waseda University
• 著者名: Hiroyuki, Akasaka; Shin-yaAbe; Masao, Yanagisawa; Nozomu, Togawa
• 著者名(英): Hiroyuki, Akasaka; Shin-ya, Abe; Masao, Yanagisawa; Nozomu, Togawa
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: With the miniaturization and high performance of current and future LSIs, demand for portable devices has much more increased. Especially the problems of battery runtime and device overheating have occurred. In addition, with the downsize of the LSI design process, the ratio of an interconnection delay to a gate delay has continued to increase. High-level synthesis to estimate the interconnection delays and reduce energy consumption is essential. In this paper, we propose a high-level synthesis algorithm based on HDR architectures (huddle-based distributed register architectures) utilizing multi-stage clock gating. By increasing the number of clock gating stages in each huddle, we increase the number of the control steps at which we can apply the clock gating to registers. We can determine the configuration of the clock gating with optimized energy consumption. The experimental results demonstrate that our proposed algorithm reduced energy consumption by up to 27.7% compared with conventional algorithms.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: With the miniaturization and high performance of current and future LSIs, demand for portable devices has much more increased. Especially the problems of battery runtime and device overheating have occurred. In addition, with the downsize of the LSI design process, the ratio of an interconnection delay to a gate delay has continued to increase. High-level synthesis to estimate the interconnection delays and reduce energy consumption is essential. In this paper, we propose a high-level synthesis algorithm based on HDR architectures (huddle-based distributed register architectures) utilizing multi-stage clock gating. By increasing the number of clock gating stages in each huddle, we increase the number of the control steps at which we can apply the clock gating to registers. We can determine the configuration of the clock gating with optimized energy consumption. The experimental results demonstrate that our proposed algorithm reduced energy consumption by up to 27.7% compared with conventional algorithms.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 7, p. 74-80, 発行日 2014-08-04
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会