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        <datestamp>2025-01-19T09:46:11Z</datestamp>
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          <dc:title>エンコードとマージソートを用いたMLC PCMのバーストレングス最適化手法</dc:title>
          <dc:title xml:lang="en">Burst Length Optimization in MLC PCM using Encoding and Merge Sort</dc:title>
          <jpcoar:creator>
            <jpcoar:creatorName>金, 磊</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>難波, 一輝</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Jin, Lei</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Kazuteru, Namba</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:subject subjectScheme="Other">メモリ・キャッシュ</jpcoar:subject>
          <datacite:description descriptionType="Other">近年，大規模データ，人工知能，IoT などの分野が発展している中，データの保存及び処理に対する要求も高まっている．伝統的な記憶技術には，読み書き速度，耐久性，消費電力などの面で制限があることが明らかである．特に，フェーズチェンジメモリ（PCM）は，これらの課題を克服するための重要な研究分野であると考えられている．本論文では，MLC PCM の読み書き速度に焦点を当て，書き込み回数を減らす方法を提案する．私たちは，書き込みの遅延をさらに減少させるために，データの事前符号化とメモリ制御の最適化という 2 つの追加の最適化を導入した．実験結果によると，提案手法は PCM の寿命延長において優れた性能を示し，少量のメタデータビットを使用するデータ比較書き込み（DCW）方法と比較している．さらに，ビットフリップを顕著に減少させ，書き込み効率を向上させたため，書き込みスループットは DCW に比べて最大 20%向上した．また，DCW に比べて，最大 30%の書き込み動的エネルギーも削減された．</datacite:description>
          <datacite:description descriptionType="Other">In recent years, with the development of fields such as big data, artificial intelligence (AI), and the Internet of Things (IoT), demands for data storage and processing have significantly increased. Traditional memory technologies have been revealed to have limitations in terms of read/write speed, durability, and power consumption. Phase Change Memory (PCM), especially Multi-Level Cell (MLC) PCM, is considered a critical area of research to address these challenges. This paper specifically focuses on the read/write speeds of MLC PCM and proposes methods to reduce the number of write operations. We introduced two additional optimizations: pre-encoding of data and optimization of memory control, aimed at further reducing write latency. Experimental results demonstrate that our proposed method significantly enhances the lifespan of PCM compared to the Data Comparison Write (DCW) method, which utilizes only a few metadata bits. Additionally, our method reduces bit flips and increases write efficiency, thereby improving write throughput by up to 20% over DCW. Furthermore, it reduces the dynamic energy required for writing by up to 30% compared to DCW.</datacite:description>
          <dc:publisher xml:lang="ja">情報処理学会</dc:publisher>
          <datacite:date dateType="Issued">2024-06-03</datacite:date>
          <dc:language>jpn</dc:language>
          <dc:type rdf:resource="http://purl.org/coar/resource_type/c_18gh">technical report</dc:type>
          <jpcoar:identifier identifierType="URI">https://ipsj.ixsq.nii.ac.jp/records/234560</jpcoar:identifier>
          <jpcoar:sourceIdentifier identifierType="ISSN">2188-8574</jpcoar:sourceIdentifier>
          <jpcoar:sourceIdentifier identifierType="NCID">AN10096105</jpcoar:sourceIdentifier>
          <jpcoar:sourceTitle>研究報告システム・アーキテクチャ（ARC）</jpcoar:sourceTitle>
          <jpcoar:volume>2024-ARC-257</jpcoar:volume>
          <jpcoar:issue>16</jpcoar:issue>
          <jpcoar:pageStart>1</jpcoar:pageStart>
          <jpcoar:pageEnd>6</jpcoar:pageEnd>
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