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        <identifier>oai:ipsj.ixsq.nii.ac.jp:00183957</identifier>
        <datestamp>2025-01-20T03:27:30Z</datestamp>
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          <dc:title>スキャンベース論理BISTにおけるマルチサイクルテストの中間観測FF選出手法について</dc:title>
          <dc:title xml:lang="en">Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST</dc:title>
          <jpcoar:creator>
            <jpcoar:creatorName>大島, 繁之</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>加藤, 隆明</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>王, 森レイ</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>佐藤, 康夫</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>梶原, 誠司</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Shigeyuki, Oshima</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Takaaki, Kato</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Senling, Wang</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Yasuo, Sato</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Seiji, Kajihara</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:subject subjectScheme="Other">テスト生成およびテスト容易化設計</jpcoar:subject>
          <datacite:description descriptionType="Other">論理 BIST における故障検出率向上のために，マルチサイクルテストにおけるフリップフロップ (FF) 値の中間観測手法が提案されている．しかし既存手法では，中間観測する FF 数，すなわち中間観測による面積オーバヘッドと故障検出率とはトレードオフの関係にある．本研究では，テスト対象回路の回路接続情報を解析することで，故障検出率向上及び回路面積増大を抑制する中間観測 FF 選出手法を提案する．評価実験により，面積オーバヘッドは既存手法から 87.5% 削減が可能であることを確認できた．</datacite:description>
          <datacite:description descriptionType="Other">A logic BIST scheme using multi-cycle test with partial observation has been proposed. In the scheme, the selection of flip-flops for partial observation plays an important role for improving the fault coverage and reducing the area overhead. This paper proposes a selection method of flip-flops for partial observation that can maximize the fault coverage under the limitation of the number of flip-flops. Experimental results show that the proposed method can obtain higher fault coverage than the existing flip-flop selection method and results in less area overhead.</datacite:description>
          <dc:publisher xml:lang="ja">情報処理学会</dc:publisher>
          <datacite:date dateType="Issued">2017-10-30</datacite:date>
          <dc:language>jpn</dc:language>
          <dc:type rdf:resource="http://purl.org/coar/resource_type/c_18gh">technical report</dc:type>
          <jpcoar:identifier identifierType="URI">https://ipsj.ixsq.nii.ac.jp/records/183957</jpcoar:identifier>
          <jpcoar:sourceIdentifier identifierType="ISSN">2188-8639</jpcoar:sourceIdentifier>
          <jpcoar:sourceIdentifier identifierType="NCID">AA11451459</jpcoar:sourceIdentifier>
          <jpcoar:sourceTitle>研究報告システムとLSIの設計技術（SLDM）</jpcoar:sourceTitle>
          <jpcoar:volume>2017-SLDM-181</jpcoar:volume>
          <jpcoar:issue>16</jpcoar:issue>
          <jpcoar:pageStart>1</jpcoar:pageStart>
          <jpcoar:pageEnd>6</jpcoar:pageEnd>
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