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        <identifier>oai:ipsj.ixsq.nii.ac.jp:00159093</identifier>
        <datestamp>2025-01-20T12:48:15Z</datestamp>
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        <jpcoar:jpcoar xmlns:datacite="https://schema.datacite.org/meta/kernel-4/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:dcndl="http://ndl.go.jp/dcndl/terms/" xmlns:dcterms="http://purl.org/dc/terms/" xmlns:jpcoar="https://github.com/JPCOAR/schema/blob/master/1.0/" xmlns:oaire="http://namespace.openaire.eu/schema/oaire/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:rioxxterms="http://www.rioxx.net/schema/v2.0/rioxxterms/" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns="https://github.com/JPCOAR/schema/blob/master/1.0/" xsi:schemaLocation="https://github.com/JPCOAR/schema/blob/master/1.0/jpcoar_scm.xsd">
          <dc:title>FPGA向けMBU訂正回路の提案</dc:title>
          <dc:title xml:lang="en">Multi bit soft error tolerant FPGA architecture</dc:title>
          <jpcoar:creator>
            <jpcoar:creatorName>中村, 祐士</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>寺岡, 拓也</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>尼崎, 太樹</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>飯田, 全広</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>久我, 守弘</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName>末吉, 敏則</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Yuji, Nakamura</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Takuya, Teraoka</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Motoki, Amagasaki</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Masahiro, Iida</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Morihiro, Kuga</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Toshinori, Sueyoshi</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:subject subjectScheme="Other">検証・信頼性</jpcoar:subject>
          <datacite:description descriptionType="Other">トランジスタサイズの微細化により，メモリに対するソフトエラーの影響が顕著になってきている．微細化がナノスケールに達した現在，一度の放射線衝突により複数のビットが反転する MBU(Multiple Bit Upset) が問題となっている．既存の対策手法として TMR(Triple Modular Redundancy) や ECC(Error Correcting Code) が挙げられるが，大きな面積を必要とするうえ，MBU に対して脆弱である．そこで本研究では，FPGA のコンフィギュレーションメモリを対象とした DMR(Double Modular Redundancy) ベースエラー訂正回路を提案する．さらに，この提案回路とビットインターリーブ法を組み合わせることで，MBU への対策を行う．この際，メモリに応じたビットインターリーブ距離を算出するために，MBU パターンとその確率を出力するソフトエラーシミュレータの開発を行う．評価より，DMR ベースエラー訂正回路は ECC や TMR と比べて面積を削減することができることを確認した．また，シミュレーションを行った結果，提案の回路構成で最適なピットインターリーブ距離は 4 であることが分かった．</datacite:description>
          <datacite:description descriptionType="Other">Due to reaching the nanoscale transistor size, effect of soft error to the memory has become conspicuous. In small device geometries, a single particle strike might affect multiple adjacent cells in a memory array resulting in a MBU (Multiple Bit Upset). Traditional fault tolerance technologies such as TMR (Triple Modular Redundancy) and ECC (Error Correcting Code) occupy the large area and have vulnerability to MBU. In this research, we propose DMR (Double Modular Redundancy) based error correct circuit and employ a combination of proposed circuit and the interleaving technique to mitigate MBU. In addition, we explain soft error simulator developed to calculate bit interleaving distance. The results show that the area of proposed circuit is the smallest when we compare the proposed circuit, ECC based error correct circuit and TMR. Simulation results show that the interleaving distance which can conceal all MBU patterns is 4.</datacite:description>
          <dc:publisher xml:lang="ja">情報処理学会</dc:publisher>
          <datacite:date dateType="Issued">2016-05-04</datacite:date>
          <dc:language>jpn</dc:language>
          <dc:type rdf:resource="http://purl.org/coar/resource_type/c_18gh">technical report</dc:type>
          <jpcoar:identifier identifierType="URI">https://ipsj.ixsq.nii.ac.jp/records/159093</jpcoar:identifier>
          <jpcoar:sourceIdentifier identifierType="ISSN">2188-8639</jpcoar:sourceIdentifier>
          <jpcoar:sourceIdentifier identifierType="NCID">AA11451459</jpcoar:sourceIdentifier>
          <jpcoar:sourceTitle>研究報告システムとLSIの設計技術（SLDM）</jpcoar:sourceTitle>
          <jpcoar:volume>2016-SLDM-176</jpcoar:volume>
          <jpcoar:issue>7</jpcoar:issue>
          <jpcoar:pageStart>1</jpcoar:pageStart>
          <jpcoar:pageEnd>6</jpcoar:pageEnd>
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