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        <identifier>oai:ipsj.ixsq.nii.ac.jp:00079578</identifier>
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          <dc:title>ハッシュ関数Luffaのハードウェア実装</dc:title>
          <dc:title xml:lang="en">Hardware Implementations of Hash Function Luffa</dc:title>
          <jpcoar:creator>
            <jpcoar:creatorName>片下, 敏宏</jpcoar:creatorName>
            <jpcoar:creatorName>佐藤, 証</jpcoar:creatorName>
            <jpcoar:creatorName>菅原, 健</jpcoar:creatorName>
            <jpcoar:creatorName>本間, 尚文</jpcoar:creatorName>
            <jpcoar:creatorName>青木, 孝文</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:creator>
            <jpcoar:creatorName xml:lang="en">Toshihiro, Katashita</jpcoar:creatorName>
            <jpcoar:creatorName xml:lang="en">Akashi, Satoh</jpcoar:creatorName>
            <jpcoar:creatorName xml:lang="en">Takeshi, Sugawara</jpcoar:creatorName>
            <jpcoar:creatorName xml:lang="en">Naofumi, Honma</jpcoar:creatorName>
            <jpcoar:creatorName xml:lang="en">Tatafumi, Aoki</jpcoar:creatorName>
          </jpcoar:creator>
          <jpcoar:subject subjectScheme="Other">一般論文</jpcoar:subject>
          <datacite:description descriptionType="Other">本論文では，次世代ハッシュ関数SHA-3の候補として提案されたスポンジ関数型のアルゴリズムLuffaに対し，複数のハードウェア・アーキテクチャを提案し，90nm CMOSスタンダードセル・ライブラリによるASIC実装およびXilinx Virtex-5とSpartan-6によるFPGA実装性能評価を行った．その結果ASICでは，回路規模14.7K～62.8Kgatesにおいてスループット3.6G～35.1Gbpsとなり，小型からきわめて高速な実装まで実現可能なことが分かった．またFPGA実装でも同様に，Virtex-5では750～1,548Slicesにおいて1.3G～7.0Gbps，Spartan-6では592～1,535Slicesにおいて1.3G～5.5Gbpsと，同様の実装性能が示された．さらに，同じスポンジ関数型でありSHA-3候補のKeccakアルゴリズムと同条件において比較したところ，Luffaはスループットにおいて同等の性能を持ちつつ，小型実装においてはおよそ半分の回路規模となり，回路構成の柔軟性が高いことが分かった．このほか，データバス構成とデータ処理の独立性が演算回路共有の効果に影響することが分かり，ハッシュ関数の設計においてハードウェア実装ではデータ処理の並列性が重要であることが明らかとなった．</datacite:description>
          <datacite:description descriptionType="Other">This paper presents hardware architectures of the hash algorithm Luffa proposed for the next generation hash standard SHA-3. The architectures were evaluated by using a 90nm CMOS standard cell library and Xilinx Virtex-5 and Spartan-6 FPGA devices. The ASIC implementations achieved a variety of circuits, from compact to very high-speed; throughputs of 3.6G-35.1Gbps with hardware resources of 14.7K-62.8Kgates. The FPGA implementations also showed high performances; throughputs of 1.3G-7.0Gbps with hardware sizes of 750-1,548Slices for Virtex-5, and throughputs of 1.3G-5.5Gbps with hardware sizes of 592-1,535Slices for Spartan-6. In comparison with other SHA-3 candidate Keccak that belongs to a category of a sponge function as same as Luffa, Luffa showed advantages in flexibility from high-speed (comparable to Keccak) to compact (half size of Keccak) hardware implementations. The results also show that data bus structure and parallelism of processing effect in design flexible.</datacite:description>
          <datacite:date dateType="Issued">2011-12-15</datacite:date>
          <dc:language>jpn</dc:language>
          <dc:type rdf:resource="http://purl.org/coar/resource_type/c_6501">journal article</dc:type>
          <jpcoar:identifier identifierType="URI">https://ipsj.ixsq.nii.ac.jp/records/79578</jpcoar:identifier>
          <jpcoar:sourceIdentifier identifierType="ISSN">1882-7764</jpcoar:sourceIdentifier>
          <jpcoar:sourceIdentifier identifierType="NCID">AN00116647</jpcoar:sourceIdentifier>
          <jpcoar:sourceTitle>情報処理学会論文誌</jpcoar:sourceTitle>
          <jpcoar:volume>52</jpcoar:volume>
          <jpcoar:issue>12</jpcoar:issue>
          <jpcoar:pageStart>3755</jpcoar:pageStart>
          <jpcoar:pageEnd>3765</jpcoar:pageEnd>
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            <jpcoar:extent>1.1 MB</jpcoar:extent>
            <datacite:date dateType="Available">2013-12-15</datacite:date>
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