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  1. 研究報告
  2. システム・アーキテクチャ(ARC)
  3. 2014
  4. 2014-ARC-209

An Asynchronous Commit DMR Architecture for Aggressive Low-Power Fault Toleration

https://ipsj.ixsq.nii.ac.jp/records/98678
https://ipsj.ixsq.nii.ac.jp/records/98678
5198166f-d026-4951-8e1b-8955128e98c2
名前 / ファイル ライセンス アクション
IPSJ-ARC14209009.pdf IPSJ-ARC14209009.pdf (939.3 kB)
Copyright (c) 2014 by the Information Processing Society of Japan
オープンアクセス
Item type SIG Technical Reports(1)
公開日 2014-02-27
タイトル
タイトル An Asynchronous Commit DMR Architecture for Aggressive Low-Power Fault Toleration
タイトル
言語 en
タイトル An Asynchronous Commit DMR Architecture for Aggressive Low-Power Fault Toleration
言語
言語 eng
キーワード
主題Scheme Other
主題 アーキテクチャ
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_18gh
資源タイプ technical report
著者所属
Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology
著者所属
Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology
著者所属
Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology
著者所属(英)
en
Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology
著者所属(英)
en
Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology
著者所属(英)
en
Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology
著者名 Yuttakon, Yuttakonkit Jun, Yao Yasuhiko, Nakashima

× Yuttakon, Yuttakonkit Jun, Yao Yasuhiko, Nakashima

Yuttakon, Yuttakonkit
Jun, Yao
Yasuhiko, Nakashima

Search repository
著者名(英) Yuttakon, Yuttakonkit Jun, Yao Yasuhiko, Nakashima

× Yuttakon, Yuttakonkit Jun, Yao Yasuhiko, Nakashima

en Yuttakon, Yuttakonkit
Jun, Yao
Yasuhiko, Nakashima

Search repository
論文抄録
内容記述タイプ Other
内容記述 Dual modular redundancy (DMR) execution is commonly used in many high-end processor platforms to tolerate the increasing transient faults caused by single event effects (SEEs) along the advances of process technology. As the operations must be performed twice to facilitate the comparison based error detection, the power consumption efficiency is always an important issue for dependable systems. To reduce the power consumption, dynamic voltage scaling (DVS), together with Razor FF, have been proposed and well used to lower the voltage to a balancing point for an optimal energy reduction. However, simply combining a DMR and Razor-FF will easily have performance impact as the synchronous committing logic in the traditional DMR architecture does not work well with the dynamic frequency in a Razor FF processor. In this research, we propose a globally asynchronous locally synchronous DMR architecture that uses dedicated clocks on each DMR module. FIFOs and delay buffers are additionally added and well controlled to guarantee the data checking inside this asynchronous system for both soft and timing error. Compared to the traditional synchronous DMR system, we can have around 10% performance improvement by this asynchronous committing scheme when a same power reduction ratio is assumed. On the other hand, voltage can be aggressively tuned in either DMR module to achieve 12% better MIPS/W without major down-gradation of the performance.
論文抄録(英)
内容記述タイプ Other
内容記述 Dual modular redundancy (DMR) execution is commonly used in many high-end processor platforms to tolerate the increasing transient faults caused by single event effects (SEEs) along the advances of process technology. As the operations must be performed twice to facilitate the comparison based error detection, the power consumption efficiency is always an important issue for dependable systems. To reduce the power consumption, dynamic voltage scaling (DVS), together with Razor FF, have been proposed and well used to lower the voltage to a balancing point for an optimal energy reduction. However, simply combining a DMR and Razor-FF will easily have performance impact as the synchronous committing logic in the traditional DMR architecture does not work well with the dynamic frequency in a Razor FF processor. In this research, we propose a globally asynchronous locally synchronous DMR architecture that uses dedicated clocks on each DMR module. FIFOs and delay buffers are additionally added and well controlled to guarantee the data checking inside this asynchronous system for both soft and timing error. Compared to the traditional synchronous DMR system, we can have around 10% performance improvement by this asynchronous committing scheme when a same power reduction ratio is assumed. On the other hand, voltage can be aggressively tuned in either DMR module to achieve 12% better MIPS/W without major down-gradation of the performance.
書誌レコードID
収録物識別子タイプ NCID
収録物識別子 AN10096105
書誌情報 研究報告計算機アーキテクチャ(ARC)

巻 2014-ARC-209, 号 9, p. 1-7, 発行日 2014-02-27
Notice
SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
出版者
言語 ja
出版者 情報処理学会
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