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A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
https://ipsj.ixsq.nii.ac.jp/records/87956
https://ipsj.ixsq.nii.ac.jp/records/879560f4c19eb-e280-4b5b-bf40-9fc8a527b823
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-SLDM13159024.pdf (915.8 kB)
2100年1月1日からダウンロード可能です。
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Copyright (c) 2013 by the Institute of Electronics, Information and Communication Engineers
This SIG report is only available to those in membership of the SIG. |
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| SLDM:会員：¥0, DLIB:会員：¥0 | ||
| Item type | SIG Technical Reports(1) | |||||||
|---|---|---|---|---|---|---|---|---|
| 公開日 | 2013-01-09 | |||||||
| タイトル | ||||||||
| タイトル | A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | FPGA高位設計 | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||
| 資源タイプ | technical report | |||||||
| 著者所属 | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属 | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属 | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属 | ||||||||
| College of Science and Engineering, Ritsuineikan University | ||||||||
| 著者所属 | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| College of Science and Engineering, Ritsuineikan University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science, Nagoya University | ||||||||
| 著者名 |
Krzysztof, Jozwik
× Krzysztof, Jozwik
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| 著者名(英) |
Krzysztof, Jozwik
× Krzysztof, Jozwik
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | Abstract—Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow of execution run on CPU and reconfigurable hardware. This paper presents a channel-based communication model tailored for such systems. The channels are abstract objects with unique and statically assigned IDs, passed as a parameter to channel access API calls. Physically, they are divided into master and slave parts located either hi SW or dynamically reconfigured with the HW task, which allows for point-to-point inter-task communication, its optimizations between a given pair of tasks and decreases the overall logic utilization in the system. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | Abstract—Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow of execution run on CPU and reconfigurable hardware. This paper presents a channel-based communication model tailored for such systems. The channels are abstract objects with unique and statically assigned IDs, passed as a parameter to channel access API calls. Physically, they are divided into master and slave parts located either hi SW or dynamically reconfigured with the HW task, which allows for point-to-point inter-task communication, its optimizations between a given pair of tasks and decreases the overall logic utilization in the system. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AA11451459 | |||||||
| 書誌情報 |
研究報告システムLSI設計技術（SLDM） 巻 2013-SLDM-159, 号 24, p. 1-6, 発行日 2013-01-09 |
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| Notice | ||||||||
| SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
