Accurate I/O Buffer Impedance Self-adjustment using Threshold Voltage and Temperature Sensors

• Item type: SIG Technical Reports(1)
• 公開日: 2012-11-19
• タイトル: Accurate I/O Buffer Impedance Self-adjustment using Threshold Voltage and Temperature Sensors
• タイトル / 言語: en
• タイトル: Accurate I/O Buffer Impedance Self-adjustment using Threshold Voltage and Temperature Sensors
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 低消費電力設計
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Dept.of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者所属: Dept.of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者所属: Dept.of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者所属: Dept.of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者所属(英): en
• 著者所属(英): Dept.of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者所属(英): en
• 著者所属(英): Dept.of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者所属(英): en
• 著者所属(英): Dept.of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者所属(英): en
• 著者所属(英): Dept.of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者名: Zhi, Li; Hiroshi, Tsutsui; Hiroyuki, Ochi; Takashi, Sato
• 著者名(英): Zhi, Li; Hiroshi, Tsutsui; Hiroyuki, Ochi; Takashi, Sato
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: With the increased operating frequency and the reduction of feature size, achieving low error-rate data transmission between LSIs is an important field of research. In particular, input/output (I/O) impedance matching, as one of the necessary technologies for high-speed transmission, is strongly required. In this paper, we propose an architecture of output buffer whose impedance is self-adjustable against process variation and temperature characteristic of MOS transistors. The proposed architecture utilizes on-chip sensor circuits to capture threshold voltages and temperatures. Based on a commercial 65nm CMOS technology, the proposed method has been verified. Without the use of reference resistor, it successfully adjusts the I/O impedance within 2.36% and 1.4% around a target of 50Ω through simulation and measurement, respectively, regardless of the process parameters and temperature.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: With the increased operating frequency and the reduction of feature size, achieving low error-rate data transmission between LSIs is an important field of research. In particular, input/output (I/O) impedance matching, as one of the necessary technologies for high-speed transmission, is strongly required. In this paper, we propose an architecture of output buffer whose impedance is self-adjustable against process variation and temperature characteristic of MOS transistors. The proposed architecture utilizes on-chip sensor circuits to capture threshold voltages and temperatures. Based on a commercial 65nm CMOS technology, the proposed method has been verified. Without the use of reference resistor, it successfully adjusts the I/O impedance within 2.36% and 1.4% around a target of 50Ω through simulation and measurement, respectively, regardless of the process parameters and temperature.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11451459
• 書誌情報: 研究報告システムLSI設計技術（SLDM）; 巻 2012-SLDM-158, 号 21, p. 1-6, 発行日 2012-11-19
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会